Physical Design Engineer (Place & Route)

Astera Labs•San Jose, CA

2d•Onsite

About The Position

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Requirements

Strong academic and technical background in electrical engineering.
A Bachelor's degree in EE / Computer Engineering is required.
8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
Entrepreneurial, open-minded behavior and can-do attitude.
Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
Block level ownership from architecture to GDSII, driving multiple complex designs to production.
Experience with Cadence and/or Synopsys physical design tools/flows.
Familiarity and working knowledge of SystemVerilog/Verilog.
Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
Experience in working with IP vendors for both RTL and hard-macro blocks.
Good scripting skills in Tcl, Python, or Perl.

Nice To Haves

Knowledge of design for test (DFT).
Familiarity with ECO methodologies and tools.
Knowledge of LVS/DRC closures.
Experience with high-speed SERDES or Ethernet PHY design integration.
Experience with clock tree synthesis optimization.
Familiarity with PCIe, CXL, or Ethernet connectivity protocols.
A Master's degree is preferred.

Responsibilities

Play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs.
Drive blocks from RTL to GDSII.
Work closely with designers, verification engineering, and engineering operations.
Floorplanning, place-and-route, timing closure, and physical sign-off.