Place and Route Design Automation Engineer

AlteraSan Jose, CA
Onsite

About The Position

Altera is seeking a motivated Place & Route (P&R) Design Automation Engineer to join our Design Methodology and Automation organization. In this role, you will contribute to the development and support of automated P&R tools, flows, and methodologies used in next-generation FPGA silicon development. You will collaborate closely with physical design, CAD, and cross-functional engineering teams to improve quality of results (QoR), runtime efficiency, and overall flow robustness. This role is well-suited for an engineer with hands-on P&R or physical design experience who is looking to deepen technical expertise in semiconductor design automation.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, with 3+ years of industry experience in semiconductor design or design automation.
  • 3+ years of hands-on experience in Place & Route (P&R), physical design, or design automation within FPGA or ASIC development environments.
  • 3+ years of experience working with Place & Route tools and strong applied knowledge of P&R algorithms, methodologies, and design flows.
  • 3+ years of experience using industry-standard EDA vendor tools (e.g., Synopsys and Cadence P&R tool suites) in production design environments.
  • 3+ years of strong coding experience in Tcl, Perl, and Python for automation, scripting, and tool integration.
  • 3+ years of experience working in Unix/Linux development environments.
  • 3+ years of experience applying physical design fundamentals, including floorplanning, placement, clocking, routing, and static timing analysis (STA).
  • 3+ years of experience debugging and resolving tool, flow, or design issues in a collaborative engineering environment.
  • 3+ years of experience collaborating with cross-functional and/or multi-geo engineering teams to support design execution.

Responsibilities

  • Work on Place & Route tools, flows, and methodologies for FPGA silicon design development.
  • Contribute to the development of new methodologies for next-generation Place & Route flows and tool enhancements.
  • Help maintain and improve existing P&R automation flows and infrastructure.
  • Provide end-user support for flow tools, including debugging issues and promoting best practices.
  • Develop and enhance scripts and automation utilities to improve usability, efficiency, and scalability.
  • Support improvements in P&R quality of results (timing, power, congestion, density, and overall design closure).
  • Assist in evaluating and testing new P&R tool capabilities and methodologies.
  • Identify design or flow bottlenecks and implement practical optimizations.
  • Collaborate closely with multi-geo teams across physical design, RTL, synthesis, and CAD to ensure robust end-to-end flow support.
  • Document methodologies, flow updates, and usage guidelines.

Benefits

  • Incentive opportunities that reward employees based on individual and company performance.
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