Physical Design Engineer

Apple•Waltham, MA

1d•Onsite

About The Position

Contribute to all phases of physical design of high performance PHY design from RTL to delivery of final GDSII. Generate block/chip level static timing constraints. Build full chip floorplan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct-by-construction designs. Assist in flow development for chip integration. Perform PnR using Cadence Innovus and Prime Time tool. 40 hours/week.

Requirements

Master’s degree or foreign equivalent in Electrical Engineering or related field.
Modeling and Characterizing Digital CMOS devices
Working on logic gates, latches, PLA, ROM and RAMs.
Performing design, layout and fabrication of a CMOS mixed signal Integrated Circuit
Performing Static Timing Analysis and timing validation
Analyzing interconnect and parasitic elements
Using System Verilog for Hardware Verification
Designing and analyzing High-Speed Logic and memory

Responsibilities

Contribute to all phases of physical design of high performance PHY design from RTL to delivery of final GDSII.
Generate block/chip level static timing constraints.
Build full chip floorplan including pin placement, partitions and power grid.
Develop and validate high performance low power clock network guidelines.
Perform block level place and route and close the design to meet timing, area and power constraints.
Generate and Implement ECOs to fix timing, noise and EM IR violations.
Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers.
Participate in establishing CAD and physical design methodologies for correct-by-construction designs.
Assist in flow development for chip integration.
Perform PnR using Cadence Innovus and Prime Time tool.