Physical Design Engineer

Ambarella • Headquarters, KY

1d

About The Position

The Physical Design Engineer will be an integral part of the physical design team, responsible for all aspects of physical design implementation and verification tasks for Ambarella’s cutting edge low power AI SoC, from Netlist to GDSII. This role encompasses various phases of the SoC implementation process, including floor-planning, auto place and route, static timing analysis, eco implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification (LVS/DRC/DFM) at both block and full chip levels. Ambarella focuses on AI Vision Processors for Edge Applications, making cameras smarter by extracting valuable data from high-resolution video streams, with target applications in autonomous vehicles, intelligent video surveillance, self-flying drones, smart wearable cameras, and 360-degree immersive video.

Requirements

• BS/MS in EE/computer science or equivalent experience
• 3- 5+ years’ experience
• Good understanding in VLSI digital design/Layout/Timing closure
• Basic knowledge on circuit design, device delays, and timing at gate-level
• Familiar with industry EDA tools such as Cadence Innovus/Quantus/Tempus, Synopsys Fusion Compiler/ICC2/StarRC/Primetime and Mentor Calibre
• Proficient programming and scripting skills (Perl, Python, TCL, C-shell, make)
• Experience with Hardware Design Languages like Verilog, VHDL
• Self-motivated team worker, good verbal and written interpersonal skills
• Solid understanding of hierarchical physical design strategies, methodologies and nanometer advanced node technology issues
• Hands-on experience in STA including multi-mode multi-corner analysis and ability to analyze and fix critical timing issues

Nice To Haves

• Experience with Cadence Innovus/Genus/Conformal and Synopsys Primetime/StarRC
• Proven track record of delivering tape-out quality GDSII with silicon success in sub 10 nm

Responsibilities

• Perform all aspects of physical design implementation and verification tasks for Ambarella’s cutting edge low power AI SoC from Netlist to GDSII
• Execute floor-planning
• Conduct auto place and route
• Perform static timing analysis
• Implement ECOs
• Conduct signal integrity analysis
• Perform EM/IR analysis
• Execute formal verification
• Perform physical layout verification (LVS/DRC/DFM) at block and/or full chip level

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level