Wireless SOC Design Verification Engineer

Apple • San Diego, CA

1d

About The Position

Apple is hiring a Senior Wireless SOC Verification Engineer to verify wireless SoC designs, including the successor to the N1 wireless chip used across new iPhones. The engineer owns their verification scope from test planning through signoff and may deepen expertise in particular IPs and subsystems or broaden across IPs, subsystems, and integration levels, from block verification to top-level SoC integration, across different projects.

The role covers the Power Management Unit, CPU subsystem, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, and peripherals such as SPI and UART. The engineer selects simulation, formal verification, or other suitable approaches based on the design. They verify power intent using UPF within their scope, including where low-power behavior crosses IP boundaries. The team is developing its approach to AI-assisted verification, and the engineer will help identify useful applications such as test generation, debug, and verification closure.

Requirements

• Bachelor of Science degree.
• At least 10 years of relevant industry experience.
• Proven experience working through the full ASIC cycle from concept to tape-out to bring-up.
• Experience with test planning, testbench implementation, test sequence creation and debugging, and coverage closure.
• Expertise in SystemVerilog coding and UVM methodology.

Nice To Haves

• Hands-on UVM verification experience with PCIe, bus fabric, NOC, AHB, or AXI-based bus architectures.
• Experience verifying IP or top-level integration for a WiFi or Bluetooth SoC.
• Experience with formal verification.
• In-depth knowledge and experience with low-power design, UPF integration, boot-up, power-cycling, and hardware/firmware interaction verification.
• Experience taping out large SoC systems with embedded processor cores.
• Excellent communication and problem-solving skills, a collaborative approach, and interest in diverse challenges.

Responsibilities

• Own verification scope end-to-end, from test planning through signoff.
• Work across the Power Management Unit, CPU subsystem, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, and peripherals such as SPI and UART.
• Select simulation, formal verification, or another appropriate verification approach based on the design.
• Verify power intent using UPF across the engineer’s area of responsibility, including beyond individual IP blocks.
• Help determine where AI-assisted verification can be applied, including test generation, debug, and verification closure.
• Contribute to verification at block and top-level SoC integration levels, as project needs and development opportunities allow.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior