SOC Design Verification Engineer

Apple • San Diego, CA

9h

About The Position

Apple’s wireless SOC organization develops wireless silicon, emphasizing energy-efficient design and technologies that improve the product experience. The team spans RF/Analog, Systems/PHY/MAC, VLSI/RTL design and integration, emulation, design verification, test and validation, and firmware/software engineering.

The Wireless SOC Design Verification Engineer performs pre-silicon RTL verification at the block, subsystem, and top-level SOC, owning verification scope from test planning through coverage closure and signoff. The role works closely with architects, designers, and firmware engineers to develop reusable testbenches and verification environments using modern, metric-driven methods. Potential areas include power management, CPU subsystems, DMA, on-chip debug, PCIe, bus fabric, boot and secure-boot sequencing, MAC-PHY verification, radio integration, and peripherals such as SPI. The engineer selects simulation, formal, or other suitable verification approaches and verifies power intent using UPF where applicable. The scope may grow deeper within particular IPs and subsystems or broader across IPs and SOC integration. The team is also exploring applications of AI-assisted verification, including test generation, debug, and coverage closure.

Requirements

• Bachelor’s degree.
• Hands-on experience across the verification cycle, including test planning, testbench implementation, test creation and debug, and coverage closure.
• Strong SystemVerilog and Verilog skills.
• Solid working knowledge of UVM.
• Problem-solving and debugging skills with constrained-random verification.
• Understanding of digital logic design, SOC architecture, and microarchitecture.

Nice To Haves

• Experience taking at least one ASIC/SOC from concept through tape-out.
• Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment.
• Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols.
• Experience with low-power verification, UPF, boot-up, power-cycling, and hardware/firmware interaction.
• Experience with SystemVerilog Assertions (SVA) and/or formal tools such as JasperGold.
• Experience defining coverage space and writing coverage models.
• Experience with embedded CPU verification and programming in C/C++ or assembly.
• Scripting experience in Python or Perl.
• Interest in applying AI/ML to verification workflows.
• Strong teamwork and communication skills and willingness to take on diverse challenges.

Responsibilities

• Perform pre-silicon RTL verification at the block, subsystem, and top-level SOC.
• Own verification scope from test planning through coverage closure and signoff.
• Work with architects, designers, and firmware engineers.
• Build reusable testbenches and verification environments using metric-driven methodology.
• Verify applicable areas such as power management, CPU subsystems, DMA, on-chip debug, PCIe, bus fabric, boot and secure-boot sequencing, MAC-PHY, radio integration, and peripherals such as SPI.
• Choose appropriate verification approaches, including simulation or formal methods.
• Verify power intent using UPF within the assigned scope.
• Help identify effective uses of AI-assisted verification, such as test generation, debug, and coverage closure.

What This Job Offers

• Job Type: Full-time