SoC Design Verification Engineer

Intel Corporation•Santa Clara, CA

1d•$105,650 - $149,150•Hybrid

About The Position

Intel is hiring an entry-level engineer for its Server SoC Design Validation team, working on next-generation Xeon server SoCs and IPs. The role performs functional logic verification and emulation validation of integrated SoCs to ensure designs meet specifications. It develops and executes scalable, reusable verification plans, test benches, and environments for blocks, subsystems, and SoCs, and uses emulation and system simulation to verify designs, analyze power and performance, and uncover bugs. The engineer reproduces, investigates, and debugs pre-silicon issues; implements corrective measures; and works with architecture, microarchitecture, RTL development, post-silicon, and physical design teams to improve verification of complex features. The role documents test plans and leads technical reviews, incorporates security activities into test plans and regression/debug tests, and maintains and improves verification infrastructure and methodology. It also applies lessons from post-silicon validation to update coverage plans for future products.

Requirements

Master's degree in electrical engineering, computer science, engineering, or a related field.
At least 10 months of experience with silicon design and/or validation/verification.
At least 10 months of experience with x86 architecture.
At least 10 months of design and validation experience with global domains such as Reset, Clock, Fuse, GPIO, and MPP.
Self-reliance in taking issues to closure with internal and external partners.
Ownership of assigned tasks.
Problem-solving, communication, teamwork, and quick-learning abilities, with openness to learning and teaching efficient validation execution techniques.

Nice To Haves

Knowledge or experience in design and/or design verification, including developing, maintaining, and executing complex IPs and/or SoCs.
Strong debugging skills.
Robust understanding of cache coherency principles in multiprocessor SoCs and experience with layered protocols, including transaction, data link, and PHY layers.
Experience with UVM/SystemVerilog constrained-random, coverage-based design verification and formal verification methodology.
Experience across the complete verification lifecycle: verification architecture, test planning, execution, debugging, and coverage closure.
Experience developing validation test suites and continuously improving existing validation test suites and methodologies.
Xeon CPU pre-silicon, emulation validation, or post-silicon validation experience.
Experience with one or more scripting languages for automation.

Responsibilities

Perform functional logic verification and emulation validation of integrated SoCs to ensure designs meet specifications.
Define and develop scalable, reusable block, subsystem, and SoC verification plans, test benches, and verification environments that meet coverage goals and conform to microarchitecture specifications.
Execute verification plans and define and run emulation and system simulation models to verify designs, analyze power and performance, and uncover bugs.
Reproduce, root-cause, and debug issues in the pre-silicon environment.
Find and implement corrective measures to resolve failing tests.
Collaborate with SoC architects, microarchitects, full-chip architects, RTL developers, post-silicon teams, and physical design teams to improve verification of complex architectural and microarchitectural features.
Document test plans and drive technical reviews of plans and proofs with design and architecture teams.
Incorporate and execute security activities in test plans, including regression and debug tests, to ensure security coverage.
Maintain and improve functional verification infrastructure and methodology.
Use post-silicon validation learnings to address missing pre-silicon coverage and propagate updates to future products.