SoC Design Verification Engineer

Intel•Fort Collins, CO

3d•Onsite

About The Position

As a SoC Design Verification Engineer, you will help ensure the functionality and reliability of Intel’s server SoCs through functional logic verification and emulation validation. You will verify that designs meet specifications, identify potential issues, and implement corrective measures, contributing to the development of next-generation Xeon server products. The role is part of Intel’s Data Center Group, which develops technologies and solutions for data centers. The team validates advanced Xeon server SoCs and IPs, with a focus on performance, scalability, and efficiency.

Requirements

Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering.
At least 6 months of experience in silicon design and/or validation/verification methodologies and tools. This experience may come from industry work, internships, schoolwork, classes, or research.

Nice To Haves

Experience in design verification for complex IPs and SoCs.
Knowledge of UVM/SystemVerilog constrained-random, coverage-based design verification methodologies.
Familiarity with the complete verification lifecycle, including test plan creation, bug debugging, and coverage closure.
Skills in developing validation test suites and driving continuous improvement in existing methodologies.
Understanding of cache coherency principles in multiprocessor SoCs and layered protocols.
Proficiency in scripting languages for automation.
Strong debugging skills and ability to independently resolve technical issues.
Experience with Xeon CPU pre-silicon, emulation validation, or post-silicon validation.

Responsibilities

Perform functional verification and emulation validation of integrated SoCs to ensure designs meet specifications.
Develop scalable and reusable block, subsystem, and SoC verification plans, test benches, and environments.
Execute verification plans, analyze system simulation models, and debug power and performance issues.
Root-cause failure issues and implement corrective measures in the pre-silicon environment.
Collaborate with architects, RTL developers, post-silicon teams, and physical design experts to enhance verification.
Document test plans and drive technical reviews with design and architecture teams.
Conduct regression and debug tests to integrate security activities and ensure comprehensive coverage.
Maintain and improve verification infrastructure and methodology, incorporating learnings from post-silicon validations.