Staff Design Verification Engineer – SoC and eFPGA

Analog Devices • Austin, TX

22h

About The Position

Analog Devices is seeking a Staff Design Verification Engineer to help develop next-generation eFPGA technology and the SoCs that integrate it. The role focuses on digital design verification, including UVM-based methodologies, SystemVerilog assertions, and end-to-end silicon verification. The engineer will collaborate with cross-functional teams to verify complex subsystems and support the delivery of high-quality silicon products. Prior eFPGA experience is not required, but a strong background in digital hardware design, architecture, and verification is expected.

The position is part of ADI’s Embedded FPGA team, which develops programmable hardware technology for platform SoCs and supports heterogeneous processing, hardware adaptability, and high-performance edge computing across varied markets and applications. The team enables high-speed, real-time processing and hardware flexibility as system requirements evolve.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent industry experience.
• Strong understanding of SoC architectures and industry-standard bus protocols such as AXI and AHB.
• Experience debugging RTL and firmware using simulation and waveform analysis tools.
• Hands-on experience developing UVM-based verification environments.
• Proficiency in SystemVerilog, Verilog, C/C++, and Python.
• Experience developing automation solutions and working within distributed compute environments.
• Working knowledge of SystemC and Transaction-Level Modeling (TLM).
• Strong communication and collaboration skills, including the ability to work across multidisciplinary teams.
• Solid understanding of digital design fundamentals, computer architecture, timing analysis, power analysis, process variation, and reliability considerations.

Nice To Haves

• 5+ years of experience in SoC, subsystem, or microarchitecture verification.
• Experience supporting successful silicon tape-outs in advanced process nodes such as N4, N5, or similar technologies.
• Knowledge of Functional Safety (FuSA) requirements and safety-focused hardware verification methodologies.
• Experience with FPGA or programmable logic architectures.
• Familiarity with continuous integration, regression automation, and verification productivity tools.

Responsibilities

• Partner with architecture, RTL, firmware, and software teams to understand new features and define verification strategies.
• Develop verification plans covering feature interactions, system-level behavior, and hardware/software use cases.
• Design, implement, and maintain directed and constrained-random verification environments and test suites.
• Develop SystemVerilog assertions and functional coverage models.
• Debug simulation failures, identify root causes, and work with design and firmware engineers to resolve issues.
• Analyze functional and code coverage metrics and improve verification content to meet coverage goals.
• Build and support end-to-end verification flows for eFPGA soft logic within SoCs, including RTL simulation, synthesis validation, and bitstream generation.
• Contribute to verification methodology improvements, automation, and continuous integration workflows.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior