SoC Design Verification Engineer

Apple•Austin, TX

18h

About The Position

As a Design Verification Engineer on Apple’s Silicon Engineering Group, you will contribute to verifying sophisticated SoCs for Apple’s Cellular 5G platform. You will integrate IP-level design-verification environments, develop reusable UVM testbenches, implement coverage-driven test infrastructure, deploy tools and AI/ML methodologies, and improve tape-out readiness. The role involves collaborating with product development groups across Apple and working across SoC design verification in a dynamic, cross-functional organization with evolving requirements. The position offers exposure to SoC architectures, high-speed layered protocols, low-power design methodologies, accelerated verification platforms, cellular protocols, firmware-hardware interactions, and multi-chip SoC debug.

Requirements

Bachelor of Science degree.
10 or more years of experience.
Knowledge of object-oriented programming principles and experience in an OOP-based language such as Python, C++, Java, or SystemVerilog.
Digital design experience.
Comfort with all areas of SoC design verification engineering.
Ability to work in a dynamic, cross-functional organization and adapt to evolving requirements.

Nice To Haves

MSEE, MSCS, or a higher degree.
Coursework in computer architecture or networking protocols.
Hands-on experience developing UVM-based testbenches in SystemVerilog, with applied understanding of object-oriented programming.
Experience developing a DUT reference model and verification using an HVL.
Excellent communication and problem-solving skills.
Desire to seek diverse challenges.