About The Position
We are looking for talented engineers to join the STA team. The STA Engineer works closely with multiple integration teams, including DFT, Top Level PNR, PHY designers, and PNR teams. The role is responsible for developing automated block- and full-chip-level signoff flows; full-chip timing and noise convergence and signoff; enabling hierarchical timing flows; power optimizations; generating block-level budgets and context for correlation with full chip; driving custom IP integration and custom timing-check flows; and closing work with Design, DFT, architecture, and Power teams.
Requirements
- MSEE or equivalent strong experience in static timing analysis.
- Extensive experience with one of the commercial STA tools.
- Ability to fluently speak and write in English.
- Familiarity with hierarchical design approach, top-down design, and timing and physical convergence.
- Experience with backend STA closure and signoff.
- Deep understanding of design constraints development.
- Good understanding of AC timing from specifications to implementation.
- Good understanding of DFT modes and their constraints.
- Good communication skills and ability to work as a team player.
- Ability to quickly learn flows and methods.
Nice To Haves
- Understanding of noise and signal integrity effects.
- Understanding of timing-margin fundamentals from synthesis to signoff.
- Experience with scripting.
Responsibilities
- Develop automated block- and full-chip-level signoff flows.
- Perform full-chip timing and noise convergence and signoff for high-quality TO.
- Enable hierarchical timing flows.
- Perform power optimizations.
- Generate block-level budgets and context for correlation with full chip.
- Drive custom IP integration and custom timing-check flows.
- Close work with Design, DFT, architecture, and Power teams.
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What This Job Offers
Job Type
Full-time
