Sr Staff Engineer-DFT

Marvell Technology • Santa Clara, CA

2d • $134,390 - $201,300 • Onsite

About The Position

Marvell is seeking a senior staff DFT engineer for its Optical DSP (ODSP) team within the Connectivity Business Unit, based in Santa Clara. The team develops advanced ASICs for hyperscale data center, enterprise, and AI infrastructure markets, including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers. The engineer will work on a next-generation ODSP program and help establish methodology and flow for flagship products developed in advanced TSMC process nodes.

The role defines and implements DFT architecture for a chip block, integrates IP-level DFT, drives ATPG objectives, leads DFT sign-off, and supports silicon debug and yield learning. It also includes mentoring junior engineers and coordinating with design, verification, physical design, and test teams.

Requirements

• BS in EE/CE with 8+ years of DFT experience, or MS in EE/CE with 5+ years of DFT experience.
• DFT experience on complex SoCs, including multiple tape-outs and silicon bring-ups.
• Deep expertise in scan, compression, ATPG fault models, MBIST/repair, JTAG, and at-speed test.
• Strong DFT timing and STA knowledge.
• Proven independent problem-solving ability and mentoring experience.

Nice To Haves

• Experience with advanced process nodes, preferably 7nm and below.
• Experience with high-speed SerDes/DSP products.

Responsibilities

• Define DFT architecture and implementation for a chip block, including hierarchical DFT, test modes, and clocking.
• Plan, partition, and integrate IP-level DFT for SerDes, PLLs, memories, and third-party IP.
• Drive ATPG coverage, test-time, and pattern-count targets; optimize compression and power during test.
• Lead DFT sign-off, including DRC, simulation, timing, equivalence, and handoff to physical design and ATE.
• Debug silicon through failure isolation, diagnosis, and yield learning with Product and Test Engineering.
• Mentor junior engineers and review their work.
• Coordinate with design, verification, physical design, and test teams.
• Improve DFT methodology and automation.

Benefits

• Eligible to participate in bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
• Employee stock purchase plan with a 2-year look back.
• Family support programs.
• Mental health resources.
• Recognition and service awards.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior