Staff Engineer, DFT

Ambiq Micro, Inc. • Austin, TX

2d

About The Position

Ambiq is seeking a Staff Engineer, DFT to develop and implement design-for-test solutions for ultra-low-power SoCs based on subthreshold operation. The role covers scan insertion, boundary scan, MBIST, ATPG, low-power DFT architecture, and test infrastructure using standard EDA tools. The engineer will generate and analyze structural test vectors, improve coverage, test time, and test cost, and perform pre- and post-layout scan and MBIST simulations. The role also involves collaborating with design teams on DFT-related timing, physical, power, and logical issues, and working with test engineers to bring up test vectors on silicon.

Ambiq develops low-power semiconductor solutions for wearables, medical devices, IoT products, and AI-powered edge applications. Its teams work across design, research, development, production, marketing, sales, and operations in Austin, Hsinchu, Shanghai, Shenzhen, and Singapore.

Requirements

• Bachelor’s or master’s degree in ECE or EE and at least 8 years of experience in DFT implementation.
• Skill in DFT structures including scan (Stuck-At, At-Speed, and Path-Delay), scan compression, boundary scan, and MBIST.
• Experience creating and implementing hierarchical DFT architecture in complex SoCs.
• Experience with Low-Power DFT and MBIST.
• Experience analyzing test time and test coverage for scan and MBIST patterns.
• Experience working with a test engineering team to bring up a production test program.
• Extensive knowledge of timing concepts and constraint development.
• Experience developing scan ATPG and MBIST test benches and performing simulations in pre- and post-layout environments.
• RTL experience is required.
• Motivated, self-driven approach and attention to detail.
• Strong verbal and written English communication skills.

Nice To Haves

• Experience with scripting such as Tcl.
• Experience with GLS (gate-level simulation).

Responsibilities

• Perform scan insertion, boundary scan, MBIST, and ATPG for ultra-low-power SoCs based on subthreshold operation using standard EDA tools.
• Develop and implement low-power DFT architecture and infrastructure.
• Generate structural test vectors; analyze and improve coverage, test time, and test cost.
• Perform pre- and post-layout scan and MBIST simulations.
• Work with designers on DFT-related STA, physical, power, and logical issues.
• Work with test engineers to bring up test vectors on silicon.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior