DFT Engineer

Normal Computing Corporation • Palo Alto, CA

4d

About The Position

As a Design-for-Test (DFT) Engineer at Normal Computing, you will own the DFT architecture and implementation for next-generation, physics-inspired ASICs, from early RTL design through tapeout and silicon bring-up. You will define and drive scan/ATPG, memory built-in self-test (MBIST), and boundary-scan strategies, working closely with RTL, verification, physical design, and silicon product engineering teams.

This is a hands-on technical leadership role with end-to-end ownership of silicon testability. You will establish DFT methodologies, guide external implementation partners, and ensure designs are ready for manufacturing test. The work involves unconventional computing architectures where testability must be considered from the beginning, with the opportunity to shape DFT infrastructure for a new class of silicon.

Requirements

• 7+ years of experience in DFT implementation for complex ASICs or SoCs, including successful tapeouts.
• Hands-on expertise in scan insertion, ATPG, scan compression, fault coverage analysis, and test pattern generation.
• Experience with MBIST, boundary scan/JTAG, and DFT integration across RTL and gate-level designs.
• Proficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX, or Cadence Modus.
• Solid understanding of RTL design, synthesis, static timing analysis, and physical design considerations.
• Experience delivering manufacturing test patterns and collaborating with silicon product engineering or ATE teams.
• Strong scripting skills in Python, Tcl, or similar languages.
• Ability to independently own DFT architecture, drive cross-functional technical decisions, and communicate effectively across design, verification, and product engineering teams.

Nice To Haves

• Experience establishing DFT architecture and methodology from the ground up for a new ASIC program.
• Familiarity with IEEE 1500, IEEE 1687 (IJTAG), hierarchical DFT, and advanced scan compression techniques.
• Experience with memory redundancy, built-in self-repair (BISR), silicon diagnosis, and yield improvement.
• Experience working with external DFT implementation partners or managing outsourced DFT deliverables.
• Exposure to AI accelerators, memory-intensive architectures, or unconventional computing systems.
• Experience using AI-assisted or agentic tools to automate silicon design and verification workflows.

Responsibilities

• Define and own chip-level DFT architecture, including scan insertion, ATPG, scan compression, MBIST, boundary scan/JTAG, and test access infrastructure.
• Drive DFT insertion and integration across RTL, synthesis, and physical design, ensuring testability requirements are met without compromising power, performance, or area.
• Own DFT verification, ATPG pattern generation, fault coverage analysis, test-mode validation, and DFT signoff through tapeout.
• Partner with the Head of Silicon Product Engineering to deliver production-ready test patterns and test collateral to manufacturing partners, along with documentation for ATE integration, silicon bring-up, and diagnosis.
• Establish scalable DFT flows, automation, and best practices using industry-standard EDA tools to support future ASIC programs.
• Define technical requirements for contracted DFT work, oversee external partners, and review deliverables for quality and integration with Normal’s silicon development process.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed