Principal Engineer, DFT

kepler•San Jose, CA

1d•$250,000 - $310,000

About The Position

Kepler is seeking a highly experienced DFT Lead to own Design for Test (DFT) for its memory products. The role architects, implements, and drives a complete DFT solution through tapeout, balancing test coverage, test time, area overhead, and power. It covers DFT architecture and implementation, programmable memory BIST, repair and redundancy management, test coverage closure, and collaboration across design and post-silicon teams.

Requirements

B.Tech, M.Tech, or MS in EE, ECE, Computer Engineering, or a related field.
15+ years of hands-on DFT architecture and implementation experience on complex ASIC/SoC designs, with multiple silicon tapeouts.
Deep ATPG expertise, including stuck-at, transition, path delay, and cell-aware testing, using industry-standard DFT tools.
Strong MBIST architecture and implementation experience on large designs.
Hands-on experience designing or modifying programmable BIST engines for memory testing, including repair flow and diagnostics.
Strong knowledge of JTAG TAP controller design and boundary scan, including BSR, BSDL, and compliance.
Solid understanding of hierarchical DFT architecture, scan chain partitioning, and scan compression.
Understanding of DFT-aware RTL practices and how DFT interacts with physical design.
Experience with ATE interfaces and production test program development.
Strong scripting skills in Python, Tcl, and Perl.
Excellent communication skills and a proven ability to own complex DFT solutions end to end in a fast-paced environment.

Nice To Haves

Experience with memory test, repair, and yield learning in high-volume manufacturing.
Knowledge of DFT and test strategies for 3D innovations.
Prior startup experience with lean teams and aggressive schedules.

Responsibilities

Own DFT architecture and implementation end to end, from definition through RTL, netlist, verification, and tapeout.
Drive the design of programmable memory BIST engines, including test algorithms, address sequencing, repair flow, and fail analysis tailored to the memory architecture.
Design repair and redundancy management, including hard and soft repair, repair data storage, fail logging, and diagnostics infrastructure.
Define DFT strategy for full-scan ATPG, embedded compression, MBIST, JTAG, boundary scan, and hierarchical test integration.
Drive test coverage closure through fault models, coverage targets, and ATPG pattern optimization.
Work with architecture, RTL, physical design, packaging, and post-silicon validation teams to make DFT-aware decisions early.
Set DFT best practices, sign-off infrastructure, and documentation standards.