Principal DFT Engineer

SiTime Corporation•Santa Clara, CA

1d•$160,920 - $230,140

About The Position

SiTime is seeking a seasoned Principal DFT Engineer to lead the DFT architecture, implementation, verification, and signoff of complex digital blocks and subsystems. The successful candidate will take end-to-end ownership of DFT from architecture and specification through implementation, coverage closure, silicon bring-up, and manufacturing support. This role serves as a technical leader for DFT, shaping methodology and automation, resolving complex cross-functional challenges, and establishing engineering best practices across multiple programs. SiTime is a precision timing company whose MEMS-based programmable semiconductor solutions support applications including AI datacenters, automated driving, industrial and humanoid robots, wearables, and IoT. Its solutions aim to provide greater accuracy, smaller size, lower power, and improved reliability. The company has shipped more than 4 billion devices. The role offers base salary, eligibility for a quarterly bonus tied to innovation goals, equity grants, and benefits including a 401(k) plan, medical, dental, vision, life, parental leave, legal services, and time off plans. SiTime is an Equal Opportunity Employer and participates in the E-Verify program.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, or a related field and at least 10 years of relevant experience, or a Ph.D. and at least 6 years of relevant experience.
Hands-on experience driving DFT implementation and signoff through successful tape-outs on advanced process nodes.
Deep hands-on experience with industry-standard DFT insertion, ATPG, and verification tools, such as Siemens Tessent, Synopsys TestMAX, or Cadence Modus.
Strong scripting capability in Tcl, Perl, and/or Python applied to DFT flow automation, test pattern generation, and custom reporting.
Strong understanding of SDC timing constraints for functional, scan-shift, and capture modes, and their interaction with multi-mode, multi-corner timing closure.
Thorough knowledge of static DFT analysis, fault modeling, ATPG pattern generation, and gate-level simulation with timing.
Experience driving DFT-related timing and implementation closure with Physical Design, including scan-chain, test-clock, test-mode, and ECO-related issues through signoff.
Strong analytical and problem-solving skills, with the ability to communicate complex technical trade-offs clearly to peers and leadership.
English proficiency sufficient to communicate, collaborate, and perform job responsibilities in a professional business environment.

Nice To Haves

12 or more years of relevant digital DFT experience, including technical leadership across multiple complex tape-outs.
Experience with automotive DFT requirements and functional-safety architectures.
Experience implementing power-aware DFT methodologies to minimize shift/capture IR drop and driving flow and methodology enhancements from scratch.
Prior experience working directly with ATE test engineers on post-silicon bring-up, pattern translation, and yield debug.
Demonstrated ability to drive DFT implementation and coverage closure for multiple digital cores in parallel while maintaining schedule and signoff quality.
Experience with memory DFT, including MBIST, memory repair, and BISR methodologies.
Experience with JTAG/boundary-scan architectures and related test-access methodologies.

Responsibilities

Serve as the technical focal point for DFT, leading architecture, implementation, verification, and signoff reviews, and establishing reusable methodologies across multiple programs.
Define DFT architecture and specifications, including scan architecture, compression, test access, clocking, test modes, core wrapping, and hierarchical DFT strategy.
Implement and validate digital DFT structures, including scan insertion, OCC insertion, advanced compression architectures such as EDT and LPCT, and core wrapping.
Develop and improve automated, reproducible DFT implementation, verification, ATPG, and signoff flows to increase productivity, reduce execution risk, and ensure consistent test quality across programs.
Own ATPG generation, pattern validation, fault analysis, and coverage closure; identify and resolve testability limitations to achieve product coverage and quality targets.
Define, develop, and verify timing constraints for functional, scan-shift, capture, and other test modes.
Collaborate with RTL and Physical Design teams to identify and resolve testability issues early, meet coverage requirements, and integrate DFT implementations.
Partner with ATE and product/test engineering teams to bring up test patterns on silicon, diagnose pattern and test failures, support yield learning, and drive issues to closure.