Staff SoC DFT Engineer, HBM

Micron•Folsom, CA

4d•$146,000 - $247,000

About The Position

Micron Technology’s Heterogeneous Integration Group (HIG), within the Technology and Products Group, develops High Bandwidth Memory (HBM) solutions for AI and machine-learning applications. HBM designs stack multiple DRAM chips with a high-speed memory controller and coordinated logic chip in one package, using Through Silicon Via technology to improve memory density and bandwidth while targeting low power per bit. The Staff SoC DFT Engineer will own design-for-test (DFT) solutions for complex HBM system-on-chip base-die designs. The role is responsible for DFT architecture and implementation, supporting manufacturability, product quality, and successful silicon bring-up across current and future HBM generations. The engineer will work closely with RTL design, SoC integration, physical design, verification, product engineering, test, probe, manufacturing, CAD, and methodology teams.

Requirements

Strong hands-on experience with SoC DFT architecture and implementation, including scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG.
Experience across full RTL-to-GDS SoC flows and collaborating with synthesis, STA, and physical design teams.
Proficiency with industry-standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
Seven or more years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs.

Nice To Haves

Experience with large, complex SoCs integrating multiple IP blocks and subsystems.
Strong RTL debugging, design analysis, and problem-solving skills.
Experience using scripting languages such as Python, Tcl, or Perl for flow automation.
Familiarity with memory systems such as DRAM and HBM, and related JEDEC specifications.

Responsibilities

Own SoC-level DFT structures and implementation, including scan, MBIST, applicable LBIST, boundary scan (JTAG), and test access architectures for HBM base-die builds.
Define and drive DFT architecture early in the design cycle, aligning it with SoC integration, floorplanning, timing, power, and physical design requirements.
Implement and integrate DFT logic at block, subsystem, and full-chip levels in partnership with RTL design and SoC integration teams.
Complete and sign off DFT flows, including linting, CDC checks, DFT rule checks, ATPG readiness, and coverage closure.
Collaborate with physical design teams to optimize DFT solutions for placement, routing, timing closure, and DRC/LVS signoff.
Work with verification, product engineering, test, probe, and manufacturing teams to support testability, diagnosability, pre-silicon debugging, and post-silicon bring-up.
Partner with CAD and methodology teams to standardize and improve DFT flows.
Contribute to cross-group technical reviews, mentor engineers as appropriate, and drive innovation for future HBM generations.