Software Engineer - C++ / Digital Logic Design

Siemens•Burlington, MA

18h•$90,000 - $162,000•Hybrid

About The Position

Siemens EDA is seeking a software development engineer for its Hardware Assisted Verification (HAV) division, which develops and manufactures emulators used for functional verification of System-on-Chip circuit designs. The role is part of a team developing compiler software for Siemens EDA’s next-generation emulators. The compiler converts a circuit design’s high-level description into a low-level binary representation that can be loaded and run on emulation hardware. The engineer will develop and improve compiler functionality that analyzes customer designs and maps them to emulator resources. Work includes analyzing clock and data networks, partitioning, placing, and synthesizing logic. The role involves designing and implementing new functionality, supporting existing functionality, writing system-level tests using software simulation, and developing new testing methods. Most development is in C++ on Linux, with collaboration across software and Veloce hardware teams in an international, multi-site development environment. Candidates must be able to work on-site from the Burlington, Massachusetts office. The posting also describes a hybrid work mode. Employment is contingent on verifying U.S. Person status or obtaining any necessary export license, as the position is subject to U.S. export control requirements under ITAR and/or EAR.

Requirements

BS, MS, or PhD in Computer Science or Computer Engineering.
0 to 3 years of industry software development experience developing large C++ applications as part of a team.
Demonstrated experience with algorithm and data structure design.
Understanding of gate-level digital logic design.
Ability to excel in team-oriented development and work independently.
Must be able to work on-site from the Burlington, MA office.
Must verify U.S. Person status or obtain any necessary export license for work subject to ITAR and/or EAR.

Nice To Haves

Experience in EDA software development, especially timing analysis, synthesis, design partitioning, or placement.
Software engineering skills and experience using Unix/Linux.
Demonstrated experience with software testing methods.
Experience using hardware description languages such as Verilog or VHDL.
Experience using software simulation tools such as ModelSim.
Knowledge of scripting languages such as Python or shell script.

Responsibilities

Develop and improve compiler functionality that analyzes customer designs and maps them onto emulator resources.
Analyze clock and data networks and perform partitioning, placement, and logic synthesis to support design mapping.
Participate in the design and implementation of new compiler functionality.
Support current compiler functionality.
Write system-level tests that use software simulation and develop new testing methods.
Collaborate with other software teams and Veloce hardware teams in an international, multi-site development environment.