Logic Design Engineer

Microsoft • Raleigh, NC

1d • $102,100 - $219,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) powers Microsoft’s expanding cloud infrastructure and delivers foundational technologies for its online businesses and Azure platform. The Compute Silicon & Manufacturing Engineering (CSME) organization designs, develops, manufactures, and packages Microsoft computer chips, including Azure Cobalt, and supports the quality, scale, delivery, cost, and sustainability of cloud hardware manufacturing.

The Logic Design Engineer will contribute to the microarchitecture and logic design of system-on-chip (SoC) clock controllers. The role includes developing and integrating RTL functional blocks, running design-quality checks, collaborating across engineering teams, and helping deliver qualified physical partitions and high-quality designs on schedule. The engineer will also use AI and automation to improve efficiency and support functional testing and debugging at IP and SoC levels.

Candidates must meet Microsoft, customer, and/or government security screening requirements, including a Microsoft Cloud Background Check. The position involves access to export-controlled information, so citizenship or other qualifying protected status will be verified as a condition of employment.

The typical U.S. base pay range is USD $102,100–$202,200 per year. For specific work locations in the San Francisco Bay Area and New York City metropolitan area, the range is USD $133,800–$219,200 per year. Certain roles may be eligible for benefits and other compensation. Applications will be accepted on an ongoing basis until the position is filled; the posting will remain open for at least five days.

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or bachelor's degree in one of these fields and at least 2 years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Provide proof of citizenship, U.S. permanent residency, or other qualifying protected status for assessment of eligibility to access export-controlled information; citizenship or status will be verified with valid documentation.

Nice To Haves

• At least 2 years of logic design experience.
• Knowledge of logic design flow, including low-power analysis, UPF, RTL coding, synthesis, timing constraints, and timing closure.
• At least 2 years of experience designing clock controller IP.
• Proficiency in Verilog/SystemVerilog coding constructs.
• Knowledge of front-end tools, including VCLP, Verilog simulators, connectivity tools, low-power static checkers, and linting tools.
• Demonstrated experience and knowledge of clock crossings and power/UPF in design.
• Familiarity with industry-standard interface protocols such as ARM.
• Familiarity with formal equivalence verification and power analysis.
• Good verbal and written communication skills.

Responsibilities

• Develop and integrate RTL for functional blocks related to SoC clock controllers.
• Perform design quality checks, including timing closure, lint, clock-domain crossing (CDC), synthesis, and low-power intent checks.
• Use AI to improve process and development efficiency.
• Interface with verification teams to ensure functional correctness.
• Collaborate with physical design, design-for-test, and other teams to deliver qualified physical partitions, evaluate tradeoffs, and provide high-quality designs.
• Write basic tests and debug block functionality and features at IP and SoC levels as needed.
• Automate tasks using scripting to improve efficiency.
• Deliver high-quality functional blocks on schedule and with professional integrity.
• Challenge the status quo with a growth mindset.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level