STA & Custom Logic Design Engineer

Apple • Sunnyvale, CA

2d

About The Position

The Analog/Mixed Signal Design team is seeking a self-motivated engineer to perform timing analysis on custom design circuits, deliver timing views to integration teams, and develop custom logic design in analog/mixed-signal circuits. The engineer will work closely with custom design engineers and cross-functional teams at the silicon and module levels, contributing to the development and performance optimization of custom mixed-signal designs.

Requirements

• Bachelor’s degree and a minimum of 10 years of relevant industry experience.
• Solid understanding of timing analysis concepts, including setup/hold time calculation, POCV on timing paths, timing constraints, transistor-level delay characterization, and rise/fall time balancing.
• Experience in timing analysis and verification for high-speed designs such as SerDes and ADC.
• In-depth knowledge and analytical understanding of mixed-signal design techniques.
• Strong track record of delivering silicon IPs with design and verification.
• Proficiency in circuit modeling and simulation, including SPICE models and worst-case corner selection.

Nice To Haves

• Master’s degree with 8 or more years of relevant industry experience.
• Experience with STA tools such as NanoTime, PrimeTime, or Tempus.
• Experience in analog/mixed-signal circuit design from architecture through fundamental implementation.
• Experience in SRAM design.
• Experience generating and managing timing/SDC constraints.
• Good understanding of tool algorithms for noise glitch, cross-talk delay, and margining with POCV.
• Proficiency in scripting languages such as Python, Tcl, or Perl.

Responsibilities

• Perform timing analysis on custom design circuits.
• Deliver timing views to integration teams.
• Develop custom logic design in analog/mixed-signal circuits.
• Work closely with custom design engineers and cross-functional teams at the silicon and module levels.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior