Senior Logic Design Engineer

Microsoft•Redmond, WA

18h•$119,800 - $261,000

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) builds infrastructure and foundational technologies for Microsoft’s online businesses and Azure platform. The Compute Silicon & Manufacturing Engineering organization designs, develops, manufactures, and packages Microsoft computer chips, including Azure Cobalt. The Silicon Logic Design team supports hardware manufacturing quality, delivery, scale, and sustainability by preparing high-quality RTL for Physical Design handoff. The Senior Logic Design Engineer will focus especially on static timing analysis, SDC constraints, and synthesis correlation and quality.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or Master's degree in one of these fields and at least 4 years of technical engineering experience; or Bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Ability to provide citizenship, U.S. residency, or other protected-status documentation for export-control eligibility assessment; citizenship is verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.
Verbal and written communication skills.

Nice To Haves

Experience in static timing analysis and logic design, including SDC/timing constraint generation, analysis, and quality assurance.
Experience setting up, debugging, and analyzing synthesis scripts and driving results toward quality targets.
Knowledge of logic design flow, including low-power analysis, UPF, RTL coding, synthesis, timing constraints, and timing closure.
Expertise in computer architecture, digital design, and IP/SoC design principles in SoC and/or IP development.
High proficiency in Verilog/SystemVerilog coding constructs.
Knowledge of front-end tools such as VCLP, Verilog simulators, connectivity tools, low-power static checkers, and linting tools.
Experience and knowledge of clock crossings and power/UPF in design.
Ability to write scripts using Perl, Tcl, Python, or similar languages.
Familiarity with industry-standard interface protocols (ARM).
Familiarity with formal equivalence verification and power analysis.

Responsibilities

Design, develop, and maintain robust timing (SDC) constraints that ensure functional correctness, hierarchical consistency, and tool compatibility while enabling PPA targets.
Use state-of-the-art tools to generate constraints and perform quality assurance for Physical Design and STA consumption.
Collaborate with and support Physical Design, STA, and DFT teams by providing collaterals from initial RTL handoff through tape out.
Analyze and debug synthesis results to optimize RTL and achieve PPA targets.
Automate tasks using scripting to improve efficiency.
Use AI to improve process and development efficiency.
Grow micro-architectural knowledge and contribute to unit, subsystem, and SoC micro-architecture.
Develop and integrate RTL for functional blocks.
Perform design quality checks, including timing closure, lint, CDC, synthesis, and low-power intent.
Write basic tests and debug block functionality and features at IP and SoC levels as needed.
Deliver high-quality functional blocks on schedule and with professional integrity.
Challenge the status quo with a growth mindset.
Mentor team members and summer interns.