STA & Custom Logic Design Engineer

Apple • Sunnyvale, CA

1d

About The Position

Apple’s Analog/Mixed Signal Design team is seeking a self-motivated engineer to perform timing analysis on custom design circuits, deliver timing views to integration teams, and develop custom logic for analog/mixed-signal circuits. The engineer will work with custom design engineers and cross-functional teams at the silicon and module levels, contributing to leading-edge technology and performance optimization for mixed-signal designs used in Apple products.

The role owns custom-design timing closure throughout the project cycle. It includes developing and implementing STA constraints from specifications; performing block- and chip-level static timing and noise analysis; and designing and characterizing transistor- and gate-level custom digital circuits in mixed-signal chips. The engineer will collaborate with RTL and custom design teams on timing changes and correct-by-construction designs and methodologies, assist design verification and DFT teams with functional and testing issues, and support CAD in developing and maintaining timing-verification and closure methodologies and flows.

Requirements

• Bachelor’s degree minimum.
• Solid understanding of timing-analysis concepts, including setup/hold time calculation, POCV on timing paths, timing constraints, transistor-level delay characterization, and rise/fall time balancing.
• Experience with timing analysis and verification in high-speed designs such as SerDes and ADC.
• In-depth knowledge and analytical understanding of mixed-signal design techniques.
• Strong track record of delivering silicon IPs with design and verification.
• Proficiency in circuit modeling and simulation, including SPICE models and worst-case corner selection.
• Master’s degree with 3+ years of relevant industry experience.
• Experience with STA tools such as NanoTime, PrimeTime, or Tempus.
• Experience in analog/mixed-signal circuit design from architecture through fundamental implementation.
• Experience in SRAM design.
• Experience generating and managing timing/SDC constraints.
• Good understanding of tool algorithms for noise glitch, cross-talk delay, and margining with POCV.
• Proficiency in scripting languages such as Python, Tcl, or Perl.

Responsibilities

• Perform timing analysis on custom design circuits and deliver timing views to integration teams.
• Own custom-design timing closure throughout the entire project cycle.
• Develop and implement STA constraints from specifications.
• Perform block- and chip-level static timing and noise analysis.
• Design and characterize transistor- and gate-level custom digital circuits in mixed-signal chips.
• Work with RTL and custom design teams on timing changes and propose correct-by-construction designs and methodologies.
• Assist design verification and DFT teams in debugging functional and testing issues.
• Assist CAD in developing and maintaining methodologies and flows related to timing verification and closure.
• Work closely with custom design engineers and cross-functional teams at the silicon and module levels.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level