Logic Design Engineer

Microsoft•Raleigh, NC

17h

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) builds and operates the infrastructure and foundational technologies supporting Microsoft’s online businesses and Azure. Its Compute Silicon & Manufacturing Engineering organization designs, develops, manufactures, and packages computer chips, including Azure Cobalt. The Logic Design Engineer will contribute to the microarchitecture and logic design of system-on-chip (SoC) clock controllers, supporting the development of reliable, high-quality cloud hardware.

Requirements

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a bachelor's degree in one of these fields and at least 2 years of technical engineering experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Provide proof of citizenship, U.S. permanent residency, or other protected status for assessment of eligibility to access export-controlled information; citizenship will be verified with a valid passport, with other documents accepted where applicable for lawful permanent residents, refugees, and asylees.

Nice To Haves

At least 2 years of logic design experience.
Knowledge of logic design flow, including low-power analysis, UPF, RTL coding, synthesis, timing constraints, and timing closure.
At least 2 years of experience designing clock controller IP.
Proficiency with Verilog/SystemVerilog coding constructs.
Knowledge of front-end tools, including VCLP, Verilog simulators, connectivity tools, low-power static checkers, and linting.
Demonstrated experience and knowledge of clock crossings and power/UPF in design.
Familiarity with industry-standard interface protocols such as ARM.
Familiarity with formal equivalence verification and power analysis.
Good verbal and written communication skills.

Responsibilities

Develop and integrate functional RTL blocks related to SoC clock controllers.
Perform design quality checks, including timing closure, lint, clock-domain crossing (CDC), synthesis, and low-power intent.
Use AI to improve efficiency in processes and development.
Work with the verification team to ensure functional correctness.
Work with physical design, design-for-test, and other teams to deliver qualified physical partitions, evaluate tradeoffs, and produce high-quality designs.
Write basic tests and debug block functionality and features at IP and SoC levels as needed.
Automate tasks using scripting.
Deliver high-quality functional blocks on schedule and with professional integrity.
Challenge established practices with a growth mindset.