Senior Logic Design Engineer

Microsoft•Hillsboro, OR

13h•$119,800 - $234,700

About The Position

Microsoft’s Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) team builds infrastructure and foundational technologies for Microsoft’s cloud businesses. Within SCHIE, the Compute Silicon & Manufacturing Engineering organization designs, develops, manufactures, and packages computer chips, including Azure Cobalt. The Silicon Logic Design team contributes to high-quality hardware manufacturing and cloud infrastructure by improving planning, quality, delivery, scale, and sustainability. The Senior Logic Design Engineer will drive high-quality RTL toward Physical Design handoff, with particular emphasis on static timing analysis, SDC constraints, and synthesis correlation and quality. The role works across design and implementation teams to develop and integrate RTL, maintain timing constraints, analyze synthesis results, perform design quality checks, and deliver functional blocks on schedule.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master's degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Ability to satisfy export-control eligibility requirements. The successful candidate must provide proof of citizenship, U.S. residency, or other protected status; citizenship will be verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.

Nice To Haves

Experience in static timing analysis and logic, including SDC/timing constraint generation, analysis, and quality assurance.
Experience setting up, debugging, and analyzing synthesis scripts and driving synthesis quality targets.
Knowledge of logic design flow, including low-power analysis, UPF, RTL coding, synthesis, timing constraints, and timing closure.
Demonstrated expertise in computer architecture, digital design, and IP/SoC design principles as part of SoC and/or IP development.
High proficiency in Verilog/SystemVerilog coding constructs.
Knowledge of front-end tools such as VCLP, Verilog simulators, connectivity tools, low-power static checkers, and linting tools.
Demonstrated experience and knowledge of clock crossings and power/UPF in design.
Ability to write scripts using Perl, Tcl, Python, or similar languages.
Familiarity with industry-standard interface protocols (ARM) is a plus.
Familiarity with Formal Equivalence Verification and Power Analysis is a plus.
Verbal and written communication skills.

Responsibilities

Design, develop, and maintain robust timing (SDC) constraints that ensure functional correctness, hierarchical consistency, and tool compatibility while enabling PPA targets.
Use state-of-the-art tools to generate constraints and perform quality assurance for Physical Design and STA consumption.
Collaborate with and support Physical Design, STA, and DFT teams by providing collaterals from initial RTL handoff through tape out.
Analyze and debug synthesis results to drive RTL optimization toward PPA targets.
Automate tasks using scripting to improve efficiency.
Use AI to improve efficiency in processes and development.
Continue developing micro-architectural knowledge and contribute to unit, subsystem, and SoC micro-architecture.
Develop and integrate RTL for various functional blocks.
Perform design quality checks, including timing closure, lint, CDC, synthesis, and low-power intent.
Write basic tests and debug block functionality and features at IP and SoC levels as needed.
Deliver high-quality functional blocks on schedule and with professional integrity.
Challenge the status quo with a growth mindset.
Mentor team members and summer interns.