Software Engineer - C++ / Digital Logic Design

Siemens•Burlington, MA

19h•$90,000 - $162,000•Hybrid

About The Position

Siemens EDA is hiring a software development engineer in its Hardware Assisted Verification (HAV) division, which develops and manufactures emulators for functional verification of System-on-Chip designs. The role is part of a team of emulator compiler specialists developing compiler software for Siemens EDA’s next-generation emulators. The compiler converts a circuit design’s high-level description into a low-level binary representation that can be loaded and run on emulator hardware. The engineer will develop and improve compiler functionality that analyzes customer designs and maps them onto emulator resources. This work includes analyzing clock and data networks, partitioning, placing, and synthesizing logic. The position involves designing and implementing new functionality, supporting existing capabilities, writing system-level tests using software simulation, and developing new testing methods. Most work is in C++ on Linux, with collaboration across software teams and Veloce hardware teams in an international, multi-site development environment. The position is based at the Burlington, Massachusetts office and requires on-site work. The posting also describes Siemens Software’s general flexibility between home and office work and lists the role’s work mode as hybrid. Employment is contingent on verifying U.S. Person status or obtaining any required export license because the role is subject to ITAR and/or EAR export-control requirements.

Requirements

Bachelor’s, master’s, or PhD degree in Computer Science or Computer Engineering.
0 to 3 years of industry software development experience developing large C++ applications as part of a team.
Demonstrated experience designing algorithms and data structures.
Understanding of gate-level digital logic design.
Ability to excel in team-oriented development and work independently.
Must be able to work on-site from the Burlington, Massachusetts office.
Must verify U.S. Person status or obtain any necessary export license, as employment is subject to ITAR and/or EAR requirements.

Nice To Haves

Experience in EDA software development, especially timing analysis, synthesis, design partitioning, or placement.
Software engineering skills and experience using Unix/Linux.
Demonstrated experience with software testing methods.
Experience using a hardware description language such as Verilog or VHDL.
Experience using software simulation tools such as ModelSim.
Knowledge of scripting languages such as Python or shell script.

Responsibilities

Develop and improve compiler software that analyzes customer designs and maps them onto emulator resources.
Analyze clock and data networks, and perform partitioning, placement, and logic synthesis to support design mapping onto the emulator.
Design and implement new compiler functionality and support current functionality.
Write system-level tests that use software simulation and develop new testing methods.
Collaborate with other software teams and Veloce hardware teams in an international, multi-site development environment.