SoC Design Verification Engineer

Apple • Austin, TX

20h

About The Position

Join Apple’s Silicon Engineering Group to help verify sophisticated SoCs powering its Cellular 5G platform. The role contributes to the verification effort within the silicon design group, including creating and productizing Cellular SoCs. The engineer will work across the SoC design-verification lifecycle, integrating IP-level environments, developing reusable UVM test benches and coverage-driven verification infrastructure, deploying tools and AI/ML methodologies, and improving tape-out readiness. The position involves collaboration with product development groups and with design, architecture, software, firmware, and external IP delivery teams. It offers exposure to large-scale SoC architecture, high-speed protocols, low-power design, accelerated verification platforms, cellular protocols, firmware-hardware interactions, and multi-chip SoC debug.

Requirements

• Bachelor of Science degree.
• 10+ years of experience.
• Demonstrated knowledge of object-oriented programming principles and experience with an OOP-based language such as Python, C++, Java, or SystemVerilog.
• Digital design experience.
• Hands-on experience developing SystemVerilog UVM-based test benches, with applied understanding of object-oriented programming.
• Experience developing a DUT reference model and verifying it using an HVL.
• Excellent communication and problem-solving skills, and a desire to seek diverse challenges.
• Comfort working across areas of SoC design verification in a dynamic, cross-functional organization and adapting to evolving requirements.

Nice To Haves

• MSEE, MSCS, or beyond.
• Coursework in computer architecture and networking protocols.

Responsibilities

• Build coverage-driven verification plans from specifications, and review and refine them to achieve coverage targets.
• Create IP-level module and subsystem verification plans, test benches, portable test benches, sequences, and test infrastructure.
• Architect highly reusable UVM-based test benches and integrate multi-instance VIPs, subsystem test benches, and test suites at SoC level.
• Achieve targeted coverage and collaborate with design, architecture, software, firmware, and external IP delivery teams to integrate and verify the overall SoC design.
• Work with DV methodology architects to improve verification flow.
• Integrate IP-level design-verification environments, develop tools and AI/ML methodologies, and improve chip tape-out readiness.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior