SOC Design Verification Engineer
About The Position
Apple’s wireless SOC organization develops wireless silicon, with a focus on energy-efficient design and technologies that enhance the product experience. The SOC Design Verification Engineer owns a verification scope and performs pre-silicon RTL verification at the block, subsystem, and top-level SOC, from test planning through coverage closure and signoff. The role works closely with architects, designers, and firmware engineers to develop reusable, metric-driven verification environments. Potential areas include the Power Management Unit, CPU subsystem, DMA, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, MAC-PHY verification, radio integration, and peripherals such as SPI. Verification approaches may include simulation and formal methods as appropriate. The role also verifies power intent using UPF and end-to-end WiFi and Bluetooth traffic flows from subsystem through top-level SOC integration. Engineers may deepen their expertise in particular IPs and subsystems or broaden their scope across IPs and SOC integration. The team is exploring AI-assisted verification for test generation, debug, and coverage closure.
Requirements
- Bachelor’s degree.
- Hands-on experience across the verification cycle, including test planning, testbench implementation, test creation and debug, and coverage closure.
- Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM.
- Strong problem-solving and debugging skills with constrained-random verification.
- Understanding of digital logic design, SOC architecture, and microarchitecture.
- Experience taking at least one ASIC/SOC from concept through tape-out.
- Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment.
- Great teammate with excellent communication skills and a desire to take on diverse challenges.
Nice To Haves
- Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols.
- Experience with low-power verification, UPF, boot-up, power-cycling, and hardware/firmware interaction.
- Experience with SystemVerilog Assertions (SVA) and/or formal tools such as JasperGold.
- Experience defining coverage space and writing coverage models.
- Experience with embedded CPU verification; programming in C/C++ or assembly.
- Scripting experience in Python or Perl; interest in applying AI/ML to verification workflows.
Responsibilities
- Partner with architects and designers early to develop detailed verification plans from specifications.
- Develop reusable block/IP and subsystem-level UVM testbenches and support IP integration into the SOC.
- Write directed and constrained-random tests; create and analyze coverage models and drive coverage closure.
- Debug failures, including corner cases, and manage bugs through resolution.
- Verify low-power design intent using UPF within the assigned scope.
- Verify end-to-end WiFi and Bluetooth traffic flows from subsystem level through top-level SOC integration.
- Apply formal verification where appropriate.
- Build and improve automated regression flows and contribute to verification methodology.
- Explore and apply AI-assisted verification techniques to improve team productivity.
- Participate in verification reviews and uphold coding-quality standards.
- Support post-silicon bring-up as needed.
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What This Job Offers
Job Type
Full-time
