SOC Design Verification Engineer

Apple • Irvine, CA

1d

About The Position

Apple’s wireless SOC organization develops energy-efficient wireless silicon and technologies that transform the product experience. The SOC Design Verification Engineer owns a meaningful verification scope, growing it from project to project. The role covers pre-silicon RTL verification at the block, subsystem, and top-level SOC, from test planning through coverage closure and signoff. The engineer works closely with architects, designers, and firmware engineers to build reusable testbenches and verification environments using modern, metric-driven methods.

Potential areas include the Power Management Unit, CPU subsystem, DMA, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, MAC-PHY verification, radio integration, and peripherals such as SPI. The role uses simulation, formal verification, or other approaches as appropriate to the design. It also includes verifying power intent with UPF and end-to-end WiFi and Bluetooth traffic flows from subsystem through top-level SOC integration. The engineer may develop deeper expertise in specific IPs and subsystems or broaden scope across IPs and SOC integration. The team is exploring AI-assisted verification for test generation, debugging, and coverage closure. Post-silicon bring-up support may be needed.

Requirements

• Bachelor of Science degree and a minimum of 10 years of relevant industry experience.
• Hands-on experience across the verification cycle, including test planning, testbench implementation, test creation and debugging, and coverage closure.
• Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM.
• Strong problem-solving and debugging skills with constrained-random verification.
• Understanding of digital logic design, SOC architecture, and microarchitecture.
• Experience taking at least one ASIC/SOC from concept through tape-out.
• Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment.
• Great teammate with excellent communication skills and a desire to take on diverse challenges.

Nice To Haves

• Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols.
• Experience with low-power verification, UPF, boot-up, power-cycling, and hardware/firmware interaction.
• Experience with SystemVerilog Assertions (SVA) and/or formal tools such as JasperGold.
• Experience defining coverage space and writing coverage models.
• Experience with embedded CPU verification and programming in C/C++ or assembly.
• Scripting experience in Python or Perl; interest in applying AI/ML to verification workflows.

Responsibilities

• Partner with architects and designers early to create detailed verification plans from specifications, before RTL is available.
• Develop reusable block/IP and subsystem-level UVM testbenches and support IP integration into the SOC.
• Write directed and constrained-random tests; create and analyze coverage models and drive coverage closure.
• Debug failures, including corner cases, and manage bugs through resolution.
• Verify low-power design intent using UPF within the assigned scope.
• Verify end-to-end WiFi and Bluetooth traffic flows from subsystem level through top-level SOC integration.
• Apply formal verification where appropriate.
• Build and improve automated regression flows and contribute to verification methodology.
• Explore and apply AI-assisted verification techniques to improve productivity.
• Participate in verification reviews and uphold high coding-quality standards.
• Support post-silicon bring-up as needed.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior