Silicon Packaging Technology Engineer

Meta•Sunnyvale, CA

65d•$212,000 - $294,000

About The Position

Reality Labs is delivering Meta's vision through AI-powered wearable products. The compute performance, power efficiency, and form factor requirements demand custom silicon with cutting-edge packaging solutions. We are seeking a Silicon Packaging Technology Engineer to join our team and drive advanced packaging technology from concept through productization for next-generation consumer hardware.

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
12+ years of experience in advanced silicon packaging development, process integration, and manufacturing
Ability to work with mechanical and thermal constraints to co-optimize package architecture for demanding form factors
Demonstrated cross-functional collaboration with internal teams and external partners (foundry, OSAT, substrate vendors, ODMs)
Experience taking products from concept to prototyping and production, including manufacturing specifications, vendor qualifications, and yield/cost optimization
Bachelor's degree in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, or a relevant technical field

Nice To Haves

Master's or PhD degree in a relevant engineering discipline
Experience with board-level and component-level reliability testing and qualification (JEDEC standards)
Strong DOE methodology, statistical data analysis, and process characterization skills
Experience driving failure analysis (FA) — including physical FA techniques, fault isolation, and root cause determination
Excellent problem-solving and communication skills; the ability to influence cross-functional stakeholders
Track record of successful complex package product qualification with OSATs
Experience with a broad range of packaging technologies: WLCSP, fan-out RDL, WoW, CoW, PoP, SiP, flip chip, and 3D stacking
Strong understanding of chip-package interaction (CPI), thermo-mechanical stress, and warpage management
Ability to work independently, manage multiple programs, and travel internationally (typically once per quarter)

Responsibilities

Lead development and roadmap creation for advanced and disruptive packaging technologies (hybrid bonding, TSV, fan-out, SiP, flip chip, SMT, solder ball attach, and assembly processes)
Establish and manage relationships with foundries, OSATs, substrate suppliers, and material suppliers to support package development activities
Influence and align OSAT and foundry partners' roadmaps with Meta's custom silicon packaging roadmap
Collaborate cross-functionally with internal teams (silicon design, architecture, system, thermal, mechanical) and external partners (design houses, OSATs, substrate vendors) to ensure manufacturability, integration, and reliability
Support test vehicle (TV) design, process feasibility, simulation, and design rule/DFM checks with emphasis on thermo-mechanical reliability
Drive Design of Experiments (DOEs) for initial builds, product qualification, and sustaining activities
Lead triage efforts for unexpected inline process, equipment, and quality issues; drive root cause failure analysis (FA) and corrective actions with partners
Evaluate and address chip-package interaction (CPI) effects, board-level reliability (BLR), and component-level reliability (CLR) through simulation, testing, and data analysis
Track technology gaps, reliability risks, and yield issues; compile and maintain POR, TOR, FMEA, and related KPIs
Stay updated on advanced packaging technologies and market trends and identify emerging technologies
Travel both domestically and internationally up to 10% of the time