Silicon Packaging Engineer

Meta•Austin, TX

2d•$146,000 - $209,000

About The Position

Meta is seeking an experienced Silicon Packaging Engineer to join its Ecosystem and Technical Operation team. The role supports development of custom silicon packaging for infrastructure hardware and packaging solutions optimized for AI/ML products and system-level performance. Meta’s Infrastructure team designs, builds, brings up, tests, and integrates hardware systems used in data centers worldwide, with designs published through the Open Compute Project Foundation. The engineer will prioritize competing workstreams across a cross-functional engineering environment and contribute to open, efficient machine-learning platforms. The position focuses on packaging design and technology for AI/ML and networking applications, including advanced packaging development from concept through product. It involves collaborating with internal silicon, architecture, system, design, NPI, quality, reliability, and manufacturing teams, as well as external ecosystem partners, ODMs, design houses, foundries, and OSAT companies. The engineer will evaluate packaging concepts and emerging technologies, support their integration and qualification, and provide manufacturability feedback throughout product development. International travel is typically required once per quarter. Compensation is listed as $146,000 to $209,000 per year, plus bonus, equity, and benefits.

Requirements

Bachelor’s degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
Master’s degree in Materials Science, Mechanical Engineering, Electrical Engineering, or a related field, or equivalent practical experience.
8+ years of experience in semiconductor packaging, with direct ownership of advanced packaging development, assembly processes, and manufacturing.
In-depth knowledge of flip-chip, 2.5D, and 3D packaging technologies.
Experience taking products from concept to production, including developing manufacturing specifications, qualifying vendors, and improving manufacturing efficiency and cost.
Experience communicating technical packaging decisions in writing and in reviews to cross-functional engineering and manufacturing stakeholders.
Experience working effectively with cross-functional teams.
Willingness to travel internationally, typically once per quarter.

Nice To Haves

Experience working with ODM, assembly packaging, OSAT, and foundry partners.
Knowledge of packaging and assembly industry standards.
Proven understanding of fanout advanced packaging technologies.
Hands-on experience in interposer or fanout package design for organic and inorganic interposers, with or without bridges such as CoWoS-L, CoWoS-R, EMIB, or embedded fanout bridges from OSATs.
Proven technical understanding of semiconductor packaging design, SMT processes, PCB design and layout tools, failure mechanisms, and analytical techniques.
In-depth knowledge of 2.5D and 3D packaging technologies, including silicon interposers, TSVs, microbumps, and interaction between advanced packages and board-assembly constraints.
Master’s degree or PhD in Materials Science, Mechanical Engineering, or a related discipline.

Responsibilities

Perform package design for custom silicon used in AI/ML and networking applications, including single-chip, multi-chip, and SiP/module packaging, and conduct feasibility studies and analyses to support manufacturing at ODMs.
Lead development of next-generation advanced packaging technologies from concept to product, including defining and building test vehicles with ecosystem partners.
Work with internal silicon, architecture, and system teams and with external partners, ODMs, design houses, and OSAT companies.
Perform design analyses and what-if scenarios for packaging approaches such as 2.5D/3D and heterogeneous integration to improve package form factor for future product versions.
Influence ASIC vendors’, foundries’, ODMs’, and OSAT partners’ roadmaps and align them with Meta ASIC roadmaps for advanced packaging technologies, including SMT, solder-ball attach, and other assembly processes.
Participate early in silicon/package/PCB/system co-design and ODM SMT manufacturing reviews, providing manufacturability feedback and helping incorporate technology advancements and design rules.
Create, conduct, and analyze Design of Experiments (DOE) for development and sustaining activities.
Work cross-functionally with design, NPI, quality and reliability, and manufacturing teams, and support integrating new technologies into products.
Support selection and qualification of external partners, including ODMs, OEMs, and OSATs.
Collaborate with internal and external stakeholders to integrate packaging technology into product development cycles.
Stay current on advanced packaging technology developments and market trends.
Identify and evaluate emerging technologies with potential future applications.
Travel internationally, typically once per quarter.