Silicon Engineering Manager

Accenture • Scottsdale, AZ

2d • Onsite

About The Position

Accenture LLP is hiring multiple Silicon Engineering Managers in Scottsdale, Arizona. The role contributes to ASIC and RTL functional verification, including developing and enhancing testbenches, running testcase simulations and regressions, and debugging failures. The manager works with design and architect engineers to define test plans and verification requirements, develops testcases and functional coverage, and uses coverage-driven verification methods. The role also supervises team execution and collaborates with client engineers, vendors, and SoC/SS teams to deliver functional verification requirements on time. Domestic travel of approximately 80% is required to meet client needs.

Requirements

• Bachelor’s degree in Computer Science, Technology, Computer Information Systems, Computer Applications, Engineering, or a related field.
• At least 5 years of progressive post-baccalaureate experience in the IT consulting industry.
• At least 5 years of experience using hardware description languages, including SystemVerilog and C.
• At least 5 years of experience with verification methodology, including Universal Verification Methodology (UVM).
• At least 5 years of scripting experience with Python, Unix, and YAML.
• At least 5 years of experience working with Gate Level Simulation.
• At least 5 years of experience with industry-standard simulation and debug tools, including VCS, Questa, or Verdi.
• At least 5 years of experience applying computer architecture concepts, including NoC, memories, AMBA bus protocols (AXI, APB, or AHB), and cache systems.
• At least 5 years of experience integrating and configuring third-party tools, including Synopsys and Cadence, into a testbench.
• At least 5 years of project planning experience, including identifying dependencies.
• Willingness and ability to travel domestically approximately 80% of the time to meet client needs.

Responsibilities

• Contribute to Gate Level Simulation (GLS) TestBench architecture development and ASIC design verification using provided netlists; develop or enhance testbenches, run testcase suites, and debug failures.
• Drive definition of RTL design test plans based on design specifications.
• Define, develop, and integrate testcases to verify RTL designs using SystemVerilog, UVM, C, and Python.
• Work with design and architect engineers to define, develop, and integrate testbench development needed for RTL functional verification.
• Define, develop, and integrate functional coverage using Coverage Driven Verification methodology.
• Develop C-language testcases to verify CPU-based transactions according to the test plan.
• Define, develop, and integrate random constraints to generate valid random input stimulus during daily testcase regressions.
• Supervise team execution and collaborate with client engineers, vendors, and SoC/SS teams to deliver functional verification requirements on time.

What This Job Offers

• Job Type: Full-time
• Career Level: Manager