Silicon Engineering Manager

Accenture • Scottsdale, AZ

1d • Onsite

About The Position

Accenture LLP is hiring multiple Silicon Engineering Managers in Scottsdale, Arizona. The role leads and contributes to functional verification of ASIC and RTL designs, including developing and enhancing testbenches, running simulation testcase suites, and debugging failures. It involves defining test plans, testcases, functional coverage, and random constraints, as well as supporting CPU-based transaction verification. The manager supervises team execution and collaborates with client engineers, vendors, and SoC/SS teams to deliver verification requirements on time. The position requires domestic travel approximately 80% of the time to meet client needs.

Requirements

• Bachelor’s degree in Computer Science, Technology, Computer Information Systems, Computer Applications, Engineering, or a related field.
• At least 5 years of progressive post-baccalaureate experience in the IT consulting industry.
• At least 5 years of experience utilizing hardware description languages, including SystemVerilog and C.
• At least 5 years of experience with verification methodology, including Universal Verification Methodology (UVM).
• At least 5 years of experience with Python, Unix, and YAML scripting.
• At least 5 years of experience working with Gate Level Simulation.
• At least 5 years of experience with industry-standard simulation and debug tools, including VCS, Questa, or Verdi.
• At least 5 years of experience applying computer architecture concepts, including NoC, memories, AMBA bus protocols (AXI, APB, or AHB), and cache systems.
• At least 5 years of experience integrating and configuring third-party tools, including Synopsys and Cadence, into a testbench.
• At least 5 years of project planning experience, including identifying dependencies.
• Willingness and ability to travel domestically approximately 80% of the time to meet client needs.

Responsibilities

• Contribute to Gate Level Simulation (GLS) testbench architecture and ASIC design verification using provided netlists by developing or enhancing testbenches, running testcase-suite simulations, and debugging failures.
• Drive definition of RTL design test plans based on design specifications.
• Define, develop, and integrate testcases to verify RTL designs using SystemVerilog, UVM, C, and Python.
• Work with design and architect engineers to define, develop, and integrate testbench developments required for RTL functional verification.
• Define, develop, and integrate functional coverage in the testbench using Coverage Driven Verification methodology.
• Develop C-language testcases to verify CPU-based transactions according to the test plan.
• Define, develop, and integrate random constraints to generate valid random input stimulus during daily testcase regressions.
• Supervise team execution and collaborate with client engineers, vendors, and SoC/SS teams to deliver functional verification requirements in a timely manner.

What This Job Offers

• Job Type: Full-time
• Career Level: Manager