Silicon Design-for-Test (DFT) Engineer
MatX•Mountain View, CA
•Onsite
About The Position
MatX is seeking a Silicon Design-For-Test (DFT) engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for implementation of DFT functions for performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity and other key technologies in leading-edge process nodes.
Requirements
- Hands-on experience with DFT implementation — MBIST, at-speed scan and scan compression.
- Strong knowledge of modern DFT standards and protocols: JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and Streaming Scan Networks (SSN).
- Experience or Working Knowledge of loading and validating PHY firmware via serial interfaces (SPI, I2C, or JTAG), including understanding of bootloader sequences and register map initialization.
- Solid experience integrating PHY DFT interfaces (e.g., SERDES PHY test modes, analog test buses into the SoC DFT architecture.
- Familiarity with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, or equivalent.
Nice To Haves
- Experience with system-level DFT access — hierarchical test access, test data compression, and multi-die/chiplet DFT — is a strong plus.
Responsibilities
- Design and develop functional test solutions for SERDES PHY , covering loopback, eye diagram characterization, and margin testing.
- Perform DFT integration of PHY IP blocks, including boundary scan, BIST interfaces, and test mode control signals, and develop robust pattern porting flows from IP-level to SoC-level.
- Develop and maintain firmware loading flows for PHY bring-up and test — including SPI/JTAG-based firmware download, register initialization sequences, and debug support during test program development.
- Collaborate closely with verification, firmware, and test engineering teams to develop and bring up silicon test programs from simulation to ATE.
- Execute DFT implementation and verification flows for block-level DFT insertion , including scan chain closure, ATPG pattern generation, and sign-off.
- Support test escapes root cause analysis and drive continuous improvement of DFT coverage and test quality.
Benefits
- 4 weeks PTO (accrued)
- 12 company Holidays
- up to 3 weeks remote work
- Company-subsidized Medical (Kaiser or Anthem) for employees & dependents
- Guardian Dental and Vision insurances for employee & dependents
- life insurance (employee only)
- HSA and FSA offerings via Lively
- Roth IRA/ 401K (or both) retirement plans
- up to 5% company contribution to 401K
- 100% company-paid life insurance (up to $300K)
- $1500 Professional Development Budget (per year)
- Onsite team lunch & dinner Monday - Friday
- Commute on our company Uber account, or reimburse your train rides. Either way, we pay 100% for your daily commute.
- $50/mo to use on the perk you value most
- $35/mo for cellular and $40/mo for wifi
- 100% paid mental health benefit via SpringHealth and Guardian EAP.
- Up to 12 weeks paid parental leave regardless of path to parenthood
- 10 weeks pregnancy disability leave
- flexible return-to-work hours
- Benepass reproductive health & parental benefit.
- Up to $20K/month plus a dedicated internal AI Tooling Team to support your productivity
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
Education Level
No Education Listed
