Principal Design-for-Test (DFT) Engineer

Celero Communications • Irvine, CA

7h

About The Position

Celero Communications is seeking a Principal DFT Engineer to join its silicon engineering organization. The role partners with design, verification, physical design, product, and manufacturing teams to implement robust Design-for-Test methodologies that support high-quality, high-volume production of complex ASIC and SoC products.

The engineer develops DFT architecture; implements scan, scan compression, MBIST, JTAG, and other on-chip test features; generates and validates ATPG patterns; and supports DFT integration, signoff, and manufacturing test readiness. The role also participates in silicon bring-up, failure analysis, and yield improvement efforts.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 8 years of ASIC/SoC DFT experience.
• Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
• Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
• Knowledge of Verilog/SystemVerilog and digital design fundamentals.
• Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
• Strong debugging abilities.
• Comfort working in fast-paced, cross-functional environments.
• Results-driven approach and interest in delivering high-quality silicon products.

Nice To Haves

• Experience with advanced-node semiconductor technologies.
• Hands-on experience with MBIST, compression architectures, and JTAG.
• Knowledge of timing closure, physical design impacts, and low-power design techniques.
• Experience supporting silicon validation and manufacturing production ramps.
• Strong communication and cross-functional collaboration skills.

Responsibilities

• Develop and implement DFT architecture for ASIC and SoC designs.
• Perform scan insertion, scan chain planning, and scan compression implementation.
• Generate and validate ATPG patterns and analyze fault coverage results.
• Implement and verify MBIST and other on-chip test features.
• Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
• Support JTAG and boundary-scan implementation and debug.
• Drive DFT signoff activities and manufacturing test readiness.
• Participate in silicon bring-up, failure analysis, and yield improvement efforts.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal