Design for Test Engineer

Apple • Cupertino, CA

1d • $207,673 - $225,300

About The Position

Apple Inc. is hiring a Design for Test Engineer for work in Cupertino, California, and various unanticipated locations throughout the USA. The role involves preparing project collaterals, reviewing design specifications with designers, and conducting scan dump verification at RTL level and across assigned projects. The engineer also conducts emulation-level and PAGATE-level verification, identifies and helps remediate bugs in collaboration with designers, and supports other teams with issues arising after design verification ends. The position is 40 hours per week.

The stated base pay range is $207,673–$225,300 per year. Apple employees may participate in discretionary stock programs, including restricted stock unit awards and the Employee Stock Purchase Plan. Benefits include medical and dental coverage, retirement benefits, discounted products and services, and reimbursement for certain career-related educational expenses, including tuition. The role might also be eligible for discretionary bonuses or commission payments and relocation. Benefits and compensation are subject to eligibility requirements and applicable plan terms.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering or a related field.
• Four years of experience in the job offered or a related occupation.
• Experience with bug triage and resolution management using a formal bug-tracking system such as JIRA or Radar.
• Experience verifying advanced Design for Test functions, including scan and core-level testing.
• Experience performing scan testing and waveform analysis in Synopsys Verdi using a developed model.
• Knowledge of computer architecture, including pipelining, caching, and memory management.
• Experience with SystemVerilog features such as constrained-random stimulus generation and assertion-based verification, in conjunction with Verilog.
• Experience using scripting languages such as Perl, Python, or Tcl to automate verification workflows.
• Experience analyzing hardware design specifications and SystemVerilog/Verilog RTL code, conducting specification reviews, and creating verification plans.
• Experience with failure triage and debug using waveform viewers and tools such as Verdi or DVE.
• Working knowledge of DFT principles, including scan chains and ATPG patterns.

Responsibilities

• Set up and generate project collaterals.
• Conduct design specification reviews with designers.
• Conduct scan dump verification at RTL level for assigned projects and verify scan dumps for all assigned projects.
• Conduct emulation-level verification for assigned projects.
• Conduct PAGATE-level verification for assigned projects.
• Identify bugs and work with designers to remediate them.
• Support other teams with issues that arise after design verification.
• Use bug-tracking systems to file detailed reports, track issue status, and collaborate to drive issues to closure.
• Use scripting to automate simulation setup, generate test configurations, parse log files, and create regression management scripts.
• Review hardware design specifications and RTL code, create verification plans, and identify potential design-architecture flaws.
• Debug test failures using waveform viewers and debug tools, trace root causes, and provide actionable information to design teams.
• Verify scan dumps, debug mismatches between DFT reports and simulation results, and support the link between pre-silicon verification and post-silicon testing.

Benefits

• Comprehensive medical coverage
• Dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain career-related educational expenses, including tuition
• Discretionary restricted stock unit awards
• Opportunity to purchase Apple stock at a discount through the Employee Stock Purchase Plan
• Possible discretionary bonuses or commission payments
• Possible relocation assistance

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level