Design for Test Engineer

Apple • Cupertino, CA

17h

About The Position

Apple Inc. is hiring a Design for Test Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The role reviews architecture and design specifications, develops design attributes and verification plans, and works with designers to verify design-for-test (DFT) implementation. It involves developing test benches, assertions, checkers, and directed or constrained-random tests; debugging failures; running RTL and power-aware gate-level simulations; managing bugs and coverage; and building custom test benches for power-aware designs.

The engineer generates test collateral, reports, and pattern files using design-verification test scripts, and runs playback simulations with generated patterns. Simulations may be performed at RTL and gate-netlist levels with X-propagation and UPF enabled. The role also supports schedules, cross-functional engineering efforts, verification flows, automation scripts, and regressions. The engineer works with test engineers to bring up functional and structural patterns for analog IPs and DFT features on silicon, and supports further characterization and test-time optimization. The position is 40 hours per week.

Requirements

• Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
• At least 1 year of experience in the job offered or a related occupation.
• Experience or education using VLSI design and VLSI architecture to understand complex ASIC designs.
• Experience or education using computer architecture to aid in understanding compute.
• Verilog skills for debugging and verifying designs.
• Perl, Python, or Tcl scripting to automate scripts and internal tools.
• Knowledge of CMOS devices and circuits.
• Experience with digital logic gate analysis and design.
• Experience with test automation and test methodology.
• Timing analysis skills for debugging complex timing bugs.
• Experience using synthesis and simulation to debug RTL and netlist issues.
• DFT knowledge for generating ATE patterns and ATE debugging.
• Knowledge of memory circuits to verify memory operation behavior.

Responsibilities

• Review architecture and design specifications; extract design features and develop attributes and verification plans.
• Work with designers to verify DFT implementation and run checks.
• Implement test benches, assertions, checkers, and directed or constrained-random tests.
• Debug failures, run RTL and power-aware gate-level simulations, supervise bugs, and close coverage.
• Build custom test benches for power-aware designs.
• Generate test collateral and reports.
• Perform RTL and gate-netlist simulations with X-propagation and UPF enabled.
• Generate pattern files with design-verification test scripts and run playback simulations with generated patterns.
• Handle schedules and support multifunctional engineering efforts.
• Assist with verification flows, automation scripts, and regressions.
• Work with test engineers to bring up functional and structural patterns for analog IPs and DFT features on silicon, and support further characterization and test-time optimization.

Benefits

• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Tuition reimbursement for certain formal education related to career advancement at Apple.
• Potential eligibility for discretionary bonuses or commission payments.
• Potential relocation assistance.
• Opportunity to participate in discretionary employee stock programs, including restricted stock unit awards and an employee stock purchase plan with discounted Apple stock.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level