Senior Staff Design Verification Engineer
About The Position
Renesas is seeking a highly experienced Senior Staff Design Verification Engineer to provide technical leadership in verification of leading-edge memory interface products for data center, AI, and cloud computing applications. The role supports advanced memory data buffer products, including DDR6 and future generations, and drives verification strategy and execution. The position calls for deep semiconductor design verification experience with SystemVerilog and UVM; prior DDR or memory experience is advantageous but not required. Candidates must be open to relocation to Duluth, Georgia. Remote work is not available. The engineer will lead verification activities at block and system levels, establish verification strategies and methodologies, develop and optimize UVM environments and testbenches, and drive execution through functional coverage, debugging, and coverage closure. The role includes technical decision-making, resolving complex issues, developing reusable verification practices, contributing to technical reviews, mentoring engineers, and communicating progress and risks to engineering leadership and stakeholders. Renesas describes itself as an embedded semiconductor solution provider with a global team of more than 21,000 engineers and problem solvers in over 30 countries. Its culture is described by the values Transparent, Agile, Global, Innovative, and Entrepreneurial.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.
- 10 or more years of related experience in semiconductor design verification.
- Deep semiconductor design verification experience, including technical leadership of complex verification efforts.
- Advanced proficiency with SystemVerilog and extensive hands-on experience with UVM (Universal Verification Methodology).
- Experience defining verification strategies and developing verification plans from product and design specifications.
- Strong experience developing, optimizing, and debugging UVM-based verification environments and testbenches.
- Strong experience with functional verification, coverage, checkers, test development, debugging, and coverage closure.
- Ability to independently resolve complex technical problems and make verification methodology decisions.
- Ability to provide technical guidance and mentorship to other engineers.
- Must be open to relocation to Duluth, Georgia.
Nice To Haves
- Experience with DDR4, DDR5, memory interfaces, data buffers, or other high-speed memory technologies.
- Experience leading verification efforts across multiple blocks, features, or engineering groups.
- Experience developing verification methodologies or best practices applicable beyond an individual project.
Responsibilities
- Provide technical leadership for verification of complex semiconductor designs at the block and system level.
- Define and drive verification strategies, methodologies, test plans, and coverage approaches for complex designs and features.
- Lead the development and optimization of SystemVerilog/UVM verification environments and testbenches.
- Drive verification execution, functional coverage, debugging, and coverage closure.
- Take ownership of significant verification efforts and make independent technical decisions about verification methods, techniques, and priorities.
- Work with design engineers and other technical stakeholders to ensure designs meet functional and performance requirements and are effectively verifiable.
- Analyze complex verification and design issues, determine root causes, and drive solutions.
- Anticipate technical challenges and identify improvements to verification methodologies, processes, quality, and efficiency.
- Drive development of reusable verification solutions, methodologies, and best practices for broader engineering efforts.
- Participate in and provide technical leadership during architecture, feasibility, design, and technical reviews.
- Serve as a subject matter expert in design verification and provide technical guidance on complex problems.
- Mentor and guide verification engineers across projects and experience levels.
- Coordinate with technical stakeholders across teams and disciplines to achieve verification milestones and objectives.
- Communicate verification status, technical risks, recommendations, and readiness to engineering leadership and project stakeholders.
Benefits
- Medical benefits.
- Health savings account with applicable medical plan.
- Dental insurance.
- Vision insurance.
- Health and/or dependent care flexible spending accounts.
- Pre-tax commuter benefits.
- Life insurance and AD&D.
- Pet insurance.
- Company-paid life insurance and AD&D for benefited employees.
- Long-term disability and short-term medical benefits.
- Paid sick time.
- Paid holidays.
- Accrued paid vacation.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
