Senior Design Verification Engineer

Microsoft • Raleigh, NC

2h

About The Position

Microsoft Silicon, Cloud, Hardware, and Infrastructure Engineering (SCHIE) delivers foundational technologies and infrastructure for Microsoft’s online businesses and Azure platform. The Compute Silicon & Manufacturing Engineering (CSME) organization designs, develops, manufactures, and packages computer chips, including Azure Cobalt, while supporting the quality, delivery, scale, and sustainability of Microsoft cloud hardware.

The Senior Design Verification Engineer joins a pre-silicon verification team and develops critical verification IP used across IP, subsystem, and SoC environments. The role focuses on verification of designs and the SoC coherent fabric, creating verification strategies and UVM environments, and collaborating across architecture, design, validation, and engineering teams to improve quality and find bugs earlier.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master’s degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor’s degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including a Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Provide proof of citizenship, U.S. residency, or other protected status for eligibility assessment to access export-controlled information; citizenship will be verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.

Nice To Haves

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• At least 3 years of experience working on computer architecture and SoC design and verification principles, including industry-standard HDLs such as SystemVerilog.
• At least 3 years of experience developing and using verification environments in industry-standard languages such as SVTB UVM or formal verification.
• At least 3 years of experience as part of a CPU, SoC, and/or IP development team.
• Demonstrated expertise in coherent and non-coherent fabric IPs and protocols; CPU and system-level caches; PCIe controllers and protocols; memory controllers and DDR protocols; or ARM architecture.
• Knowledge of full-chip and system-level flows and protocols.
• Proficient communication, collaboration, and teamwork skills, and ability to contribute to diverse and inclusive teams.

Responsibilities

• Own critical verification IP used across IP, subsystem, and SoC environments as an integral member of a pre-silicon verification team.
• Develop knowledge of the SoC coherent fabric and its interaction with other IPs.
• Develop verification strategies, test plans, requirements, environments, tools, and methodologies.
• Define, document, and implement a UVM verification environment from scratch, including agents and scoreboards.
• Develop tests, test generators, test benches, checkers, coverage, and other verification collateral.
• Run tests, debug failures to root cause, and recommend fixes.
• Learn and adapt in a complex and dynamic environment.
• Work with partners to improve architecture, design, verification plans and collateral, and methodology to prevent, reduce, or detect bugs sooner and more reliably.
• Share knowledge and provide guidance to team members.
• Collaborate with and influence architects, logic designers, post-silicon validators, verification engineers, and IP and tool providers.
• Embody Microsoft’s culture and values.

Benefits

• Benefits and other compensation may be available for certain roles; details are available through Microsoft’s benefits and pay information page.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior