Design Verification Engineer

Apple • Cupertino, CA

2d

About The Position

Apple Inc. is hiring a Design Verification Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The role focuses on ensuring bug-free first silicon for assigned portions of a system-on-chip (SoC) or intellectual property (IP). The engineer develops detailed test and coverage plans based on microarchitecture and creates a verification methodology and scalable, portable verification environment.

The position includes building verification environments and their components, including stimulus, checkers, assertions, trackers, and coverage. The engineer develops and executes verification plans, supports design and verification-environment bring-up, enables regressions for assigned features, and debugs test failures. The role also develops block-, IP-, and SoC-level testbenches and tracks and reports verification progress using metrics such as bugs and coverage. The stated schedule is 40 hours per week.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field.
• Experience or education utilizing SystemVerilog for constrained-random verification and functional coverage.
• Experience or education utilizing UVM to develop verification environments and implement directed and random test cases.
• Experience or education utilizing C and C++, demonstrating strong software skills in data structures and algorithms.
• Experience or education utilizing Python and Perl for test-vector generation and executable scripts.
• Experience or education utilizing EDA tools for testbench simulations, debugging, and coverage closure.
• Experience or education utilizing high-speed interface protocols to verify high-bandwidth, low-power data communication systems.
• Experience or education utilizing digital design to understand ASIC design flows and verification.
• Experience or education utilizing computer architecture to explore memory subsystems and architecture trade-off analysis.

Responsibilities

• Ensure bug-free first silicon for assigned portions of the SoC or IP.
• Develop detailed test and coverage plans based on the microarchitecture.
• Develop a verification methodology suitable for the IP and create a scalable, portable verification environment.
• Develop verification-environment components, including stimulus, checkers, assertions, trackers, and coverage.
• Develop and execute verification plans for assigned features.
• Perform design bring-up and verification-environment bring-up.
• Enable regressions for assigned features and debug test failures.
• Develop block-, IP-, and SoC-level testbenches.
• Track and report verification progress using metrics, including bugs and coverage.

Benefits

• Opportunity to participate in discretionary employee stock programs, including restricted stock unit awards.
• Opportunity to purchase Apple stock at a discount through the Employee Stock Purchase Plan, if voluntarily participating.
• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition, for formal education related to career advancement at Apple.
• May be eligible for discretionary bonuses or commission payments.
• May be eligible for relocation.

What This Job Offers

• Job Type: Full-time