Senior Design Verification Engineer

Intel Corporation•Austin, TX

1d•$190,610 - $269,100•Onsite

About The Position

As an IP Design Verification Engineer, you will help ensure the functionality and reliability of Intel intellectual property designs. You will collaborate with architecture, design, and verification teams to ensure solutions meet industry standards. The role contributes to developing technologies and products through presilicon verification, with an opportunity to work on cutting-edge projects in a collaborative environment. The engineer develops and executes verification plans, creates and maintains test benches and verification environments, and runs system simulations to verify designs, analyze power and timing, and identify bugs. The role also involves debugging failing tests, improving verification methodologies and infrastructure, documenting plans, leading technical reviews, and contributing to technical flow methodologies.

Requirements

Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field.
At least 9 years of IP functional verification experience with a bachelor's degree, 6 years with a master's degree, or 4 years with a PhD.
Hands-on experience building verification environments using SystemVerilog and UVM.
Expertise in RTL design and debugging using industry-standard tools and methodologies.
Hands-on experience verifying networking IPs/SoCs implementing RDMA (RoCEv2, iWARP, InfiniBand) or comparable reliable transport protocols, such as Ultra Ethernet Transport or TCP offload, including QP/connection state, retransmission, packet ordering, and congestion control.
Strong collaboration and communication skills for working across architecture, design, and physical teams.
Ability to lead technical reviews and drive alignment on verification strategies.
Ability to analyze and resolve complex design issues in a presilicon environment.
Passion for continuous learning, innovation, and contributing to technical excellence.

Nice To Haves

Familiarity with scripting languages such as Python or Perl to automate verification tasks.

Responsibilities

Develop and execute comprehensive verification plans to ensure IP logic meets microarchitecture specifications.
Create and maintain test benches and verification environments to achieve high coverage and reliability.
Perform system simulations to verify designs, analyze power and timing, and identify bugs in the presilicon environment.
Debug verification issues by replicating and root-causing failures and implementing corrective measures.
Collaborate with architects, RTL developers, and physical design teams to improve verification methodologies for complex features.
Document verification plans and lead technical reviews with architecture and design teams.
Maintain and improve verification infrastructure, tools, and methodologies.
Participate in defining verification infrastructure and contribute to developing technical flow methodologies (TFMs).