Senior Technical Architect

HCL Tech • Redmond, WA

1d

About The Position

Microsoft Quantum is seeking a Senior Signal and Power Integrity Engineer to optimize ASICs, packages, and PCBs for mixed-signal circuits. The role owns signal and power integrity throughout the hardware lifecycle, working across electrical, mechanical, thermal analysis, and RF engineering within the cryogenic CMOS team.

The engineer will develop signal and power integrity designs for ICs and packages, including substrates, interposers, and redistribution layers. Work spans IP evaluation during silicon architecture, package performance evaluation, interconnect stackup selection and characterization, channel and power delivery network architecture, and PCB layout oversight. The role also involves collaboration with ASIC designers, electrical engineers, and qubit measurement engineers to optimize system design.

The position is based in Redmond, Washington, with 0–25% travel. Candidates must meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check, and be eligible to access export-controlled information. The role also requires working in an AI-first environment and building AI agents or copilots to support hardware and software development activities.

Requirements

• Master’s degree in Electrical Engineering or a related field; or a bachelor’s degree in Electrical Engineering or a related field plus at least 2 years of industry or research and development experience; or equivalent experience.
• At least 4 years of experience in technical organizations in IC design and packaging environments.
• Deep knowledge of and experience applying electrical engineering fundamentals, electromagnetic theory, and coupling mechanisms in circuit or system design, analysis, or troubleshooting.
• Hands-on experience simulating and analyzing transmission lines, channel models, and signal and power integrity.
• Experience with EDA tools such as Ansys HFSS, Q3D, SiWave, Cadence PowerSI, Clarity, PowerDC, Allegro, APD, Spectre, Keysight ADS, or Synopsys Hspice.
• Experience with signal integrity analysis of interposers and/or advanced packages, such as FCBGA, chiplet-based, CoWoS, 2.5D, or 3D architectures.
• Practical experience interpreting measurements from vector network analyzers and oscilloscopes.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Provide proof of citizenship, U.S. permanent residency, or other protected status for assessment of eligibility to access export-controlled information; citizenship will be verified using a valid passport, with other documents accepted for applicable protected statuses.
• Ability to work in an AI-first environment using modern AI tools to accelerate discovery through hardware and software development.
• Ability to design and build AI agents or copilots for experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval.

Nice To Haves

• Doctorate in Electrical Engineering or a related field.
• At least 6 years of experience in power and signal integrity designing, implementing, and debugging power delivery networks for large processors, FPGAs, SoCs, or ASICs with complex power requirements.
• Experience with analog electronic circuit design.
• Knowledge of on-chip power analysis flows such as PTPX, Redhawk, or Voltus, and SoC physical design such as floor planning.
• Experience scripting for data collection and analysis, such as with Python or bash.
• Experience debugging and resolving EMI/EMC desense problems.
• Experience with IC packaging in extreme environments and/or at cryogenic temperatures.
• Strong teamwork and communication skills.
• Ability to adapt and operate effectively in a rapidly changing research environment.
• Demonstrated experience writing and documenting technical reports.
• Experience with cross-team collaboration and/or mentoring.

Responsibilities

• Own signal and power integrity for cryogenic ASICs, packages, PCBs, connectors, and cables.
• Model and simulate end-to-end high-speed channels, including transceivers, IC packages, PCBs, cross-board connectors, and cables.
• Use industry-standard tools and methods for time- and frequency-domain signal integrity analysis, including SPICE and full-wave electromagnetic analysis.
• Identify link-quality issues such as loss, reflection, and crosstalk, and resolve them across channel transition structures, including die bumps, package BGAs, PCBs, connectors, and cables.
• Interpret simulation results and provide design guidelines for board materials, stackups, transmission-line routing, component placement, and layout optimization.
• Define best practices, simulation workflows, test methodologies, signoff criteria, and laboratory equipment needs for signal and power integrity requirements.
• Collaborate with ASIC designers, electrical engineers, and qubit measurement engineers to inform and optimize system design.
• Use modern AI tools to accelerate discovery across hardware and software development.
• Design and build AI agents or copilots to assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior