Senior Mixed Signal Design Validation Engineer

NVIDIA•Santa Clara, CA

4d•$168,000 - $310,500

About The Position

NVIDIA is seeking an experienced Mixed Signal Design Validation Engineer to join its high-speed mixed signal circuits team. The role leads bring-up and characterization of complex interfaces and modules, validating high-speed I/O systems and advanced LPDDR, GDDR, and HBM memory interfaces to ensure quality and reliability. The work supports next-generation memory technologies for NVIDIA GPUs and AI computing platforms. The engineer will create validation plans and scripts, characterize analog, digital, and mixed-signal circuit blocks across process, voltage, and temperature conditions, and correlate results with simulations. The role also includes system-level validation, silicon performance and margin assessment, circuit investigation and debugging, and development of tools that improve electrical characterization and chip bring-up. The engineer collaborates with design, PISI, hardware, firmware, and memory qualification teams, and mentors new engineers. The position is offered at Level 4 or Level 5. The stated base salary ranges are $168,000–$264,500 for Level 4 and $196,000–$310,500 for Level 5. Equity and benefits are also offered. Applications will be accepted at least until November 3, 2026.

Requirements

Bachelor of Science degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field, with at least 8 years of experience.
Solid experience in silicon bring-up and debugging, particularly for high-speed memory interfaces.
Strong understanding of memory systems and specifications.
In-depth technical knowledge of mixed-signal circuits, analog and digital systems, with a focus on high-speed memory technologies.
Strong knowledge of signal integrity and power integrity.
Experience with laboratory instrumentation, including oscilloscopes, logic analyzers, spectrum analyzers, TDR, phase noise analyzers, signal generators, and BER testers.
Strong scripting skills in Python, C, or similar languages.
Experience with Git and JMP for version control and data analysis.
Ability to work in a fast-paced, dynamic environment involving multiple-chip bring-ups and system validations.
Ability to collaborate effectively with multifunctional teams.
Strong problem-solving skills and a proactive, forward-thinking approach.

Nice To Haves

Strong expertise in measurement theory and the use of test instruments, especially for memory interface validation.
Knowledge of other high-speed transceiver performance.

Responsibilities

Lead creation of validation test plans and test scripts for DDR I/O associated with LPDDR, GDDR, and HBM memory interfaces, covering required analog and digital circuits.
Characterize analog, digital, and mixed-signal circuit blocks under varying process, voltage, and temperature conditions, and correlate results with simulations.
Drive system-level validation of memory interfaces to ensure high-speed performance and quality metrics meet GPU and AI system standards.
Investigate memory I/O circuits to identify weaknesses and support circuit improvements and future architecture enhancements.
Lead debugging efforts and develop solutions to resolve unexpected bugs.
Validate silicon performance, quality, and margins to refine memory interface designs.
Develop and implement test scripts to optimize DDR I/O circuits, sub-circuits, and overall system performance.
Collaborate with mixed-signal design, PISI, hardware, firmware, and memory qualification teams to resolve issues and improve memory interface performance.
Develop tools and scripts to enhance electrical characterization and chip bring-up processes.
Mentor and train new engineers in validation practices and promote continuous improvement.