Senior Mixed Signal Design Engineer

NVIDIA•Santa Clara, CA

4d•$168,000 - $310,500

About The Position

NVIDIA is seeking a senior engineer to join its mixed-signal design team building next-generation NVLINK. The role involves developing high-speed interfaces and analog circuits, with the opportunity to take integrated circuit designs operating at data rates of 25 Gbps and higher from concept through silicon characterization. The engineer will define circuit requirements and complete designs through schematic, layout, verification, and characterization. The position supports NVIDIA product lines spanning consumer graphics, self-driving cars, and artificial intelligence.

Requirements

Master of Science in Electrical Engineering, Computer Engineering, or a related field with a strong analog-design background, or equivalent experience.
At least 5 years of industry experience in analog design.
CMOS analog/mixed-signal circuit-design experience in deep-submicron processes, especially FinFET.
Experience with Cadence's IC design environment and analog circuit-simulation tools such as Spectre, HSpice, FineSim, or XA.
Experience creating test-bench environments for component- and top-level circuit verification.
Experience with behavioral modeling of analog and digital circuits.
Strong debugging and analytical skills.
Experience with analog simulation for noise analysis, loop-stability analysis, AC/DC/transient analysis, and Monte Carlo analysis.

Nice To Haves

Strong interpersonal skills and the ability and desire to work effectively as a teammate.

Responsibilities

Develop and implement high-speed interfaces and analog circuits.
Define circuit requirements and complete designs from schematic and layout through verification and characterization.
Conduct schematic design in deep-submicron CMOS technologies using Spectre, Hspice, or similar tools.
Own circuit architecture, transistor-level design, and verification using industry-standard EDA tools such as Cadence Virtuoso.
Optimize circuits to meet system-performance specifications.
Work with layout engineers, providing detailed floorplans and guidance on matching and high-speed routing.
Support post-silicon bring-up and debugging.