Senior Mixed Signal Design Engineer

NVIDIA•Santa Clara, CA
•$136,000 - $264,500

About The Position

NVIDIA is seeking a senior engineer to join its mixed-signal design team building next-generation NVLINK. The role involves developing high-speed interfaces and analog circuits, with hands-on responsibility for taking integrated-circuit designs operating at data rates of 25 Gbps and higher from concept through silicon characterization. The engineer will define circuit requirements and complete designs across schematic, layout, verification, and characterization, while optimizing circuits for system performance. The position includes ownership of architecture, transistor-level design, and verification using industry-standard EDA tools. The engineer will work closely with layout engineers on floorplanning, matching, and high-speed routing, and will support post-silicon bring-up and debugging. The work contributes to NVIDIA product areas including consumer graphics, self-driving cars, and artificial intelligence.

Requirements

  • Master's and/or Ph.D. of Science in Electrical Engineering, Computer Engineering, or a related field with a strong analog-design background, or equivalent experience.
  • At least 2 years of industry experience in analog design.
  • CMOS analog/mixed-signal circuit-design experience in a deep-submicron process, especially FINFET.
  • Experience with design and verification tools, including Cadence's IC design environment and analog circuit simulation tools such as Spectre, HSpice, Finesim, or XA.
  • Experience creating test-bench environments for component- and top-level circuit verification.
  • Experience with behavioral modeling of analog and digital circuits.
  • Strong debugging and analytical skills.
  • Experience with analog simulation for noise analysis, loop-stability analysis, AC/DC/transient analysis, and Monte Carlo analysis.

Nice To Haves

  • Strong interpersonal skills and the ability and desire to work effectively as a teammate.

Responsibilities

  • Develop and implement high-speed interfaces and analog circuits.
  • Take integrated-circuit designs operating at 25 Gbps and higher from concept through silicon characterization.
  • Define circuit requirements and complete designs from schematic and layout through verification and characterization.
  • Conduct schematic design in deep-submicron CMOS technologies using Spectre, Hspice, or similar tools.
  • Own architecture, transistor design, and verification using industry-standard EDA tools such as Cadence Virtuoso.
  • Optimize circuits to meet system-performance specifications.
  • Provide layout engineers with detailed floorplans and guidance for matching and high-speed routing.
  • Support post-silicon bring-up and debugging.

Benefits

  • Equity
  • Benefits
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