Senior Lead, DFT and Test Engineer

Celestica • Richardson, TX

19h • Onsite

About The Position

Celestica is seeking a Sr. Lead, DFT and Test Engineer to ensure testability and maximum test coverage are embedded into hardware design long before layout freeze. In this role within our DFx Center of Excellence, you will perform in-design testability reviews, audit test point access and boundary scan chains, and model structural and functional test coverage against key manufacturing targets to drive high-yield, debug-ready releases.

Requirements

• Background in Design for Testability (DFT), board-level schematics, and high-density PCB layout checks.
• Experience evaluating boundary scan chains, debug/provisioning access, and test point accessibility.
• Practical knowledge of MTRS coverage modeling, functional test strategy, and hardware bring-up.
• 4 to 6 years in a similar role or industry.

Responsibilities

• Review schematics and PCB layouts against the core DFT rule set prior to layout freeze, documenting findings backed by technical evidence.
• Model structural and functional coverage against the Manufacturing Test Requirements Specification (MTRS) and quantify coverage gaps.
• Partner directly with hardware design and software teams to resolve testability issues through test point additions, boundary scan chain corrections, or agreed-upon design alternatives.
• Verify actual achieved coverage on the first physical test fixture and document discrepancies against pre-layout claims.
• Assist with functional test definition and early build debug in collaboration with Technical Region Leads (TRLs) and local test SMEs.
• Propose targeted DFT rule set updates derived from test escapes and post-build fixture rework.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior