DFT Lead Engineer

Broadcom • Austin, TX

2d • Onsite

About The Position

Broadcom's ASIC Product Division is seeking a Principal DFT Engineer for its Austin, Texas Development Center. The role leads DFT programs from chip-level specification through implementation and verification, culminating in production release. Work spans SoC DFT architecture, test insertion and verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics. The engineer works with Physical Design and STA teams on DFT-mode timing closure and may interact directly with external customers. Programming in TCL, Perl, Ruby, Python, C++ or similar is expected.

Requirements

• Bachelor's degree in Electrical, Electronic, or Computer Engineering and 12+ years of relevant industry experience, or a master's degree in one of those fields and 10+ years of relevant industry experience.
• Strong DFT background, such as IO and Analog DFT, ATPG, Scan, or BIST.
• Experience with scan insertion and scan compression, such as DFT Compiler or Mentor TestKompress.
• Proficiency in ATPG vector generation, simulation, and debugging, such as with TetraMax or Fastscan.
• Experience in Verilog coding, testbench generation, and simulation.
• Experience inserting and verifying Memory BIST for embedded SRAM, CAM, eDRAM, or ROM.
• Boundary scan verification and test-vector generation experience.
• Good knowledge of IEEE 1149.1 and IEEE 1149.6.
• Basic knowledge of Test-STA and constraints.
• Strong background in IEEE 1687, IJTAG, ICL, and PDL.
• Ability to work in a multidisciplinary, cross-department environment.
• Solid knowledge of analog and digital circuit design and device-physics fundamentals.
• Good understanding of silicon processing, logical and physical synthesis, and transistor reliability principles.
• Excellent problem-solving, debugging, root-cause analysis, and communication skills.
• Ability to code using TCL, Perl, Ruby, Python, C++, or similar.

Nice To Haves

• Experience working on ATE.
• Experience with SerDes, DDR, PCIe, ENET, and CXL IOBIST verification and silicon debug.
• Experience working on Tessent SSN is highly desired.

Responsibilities

• Understand Broadcom and customer DFT feature requirements and DPPM goals, and define appropriate DFT specifications for ASICs.
• Implement DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes, and other IP DFT integration.
• Work closely with STA and DI engineers to achieve design closure for test.
• Generate, verify, and debug test vectors before tape release.
• Validate and debug test vectors on ATE during silicon bring-up.
• Assist with silicon failure analysis, diagnostics, and yield improvement.
• Interface with customers and globally located physical design, test engineering, and manufacturing teams.
• Work closely with IP DFT engineers and other stakeholders.
• Debug customer-returned parts on ATE.
• Develop new DFT solutions to address testability problems in 7nm and beyond.
• Automate DFT and test-vector generation flows.

Benefits

• Discretionary annual bonus.
• Competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal