DFT Engineer

Broadcom • San Jose, CA

2d • Onsite

About The Position

Broadcom's ASIC Product Division is seeking a DFT Engineer for its San Jose, California Development Center. The role works on DFT programs from chip-level specification through implementation and verification, supporting product release to production. Activities include SoC DFT test insertion and verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement. The engineer collaborates with Physical Design and STA teams on DFT-mode timing closure and may interact directly with external customers.

Requirements

• Strong DFT background, such as IO and Analog DFT, ATPG, Scan, or BIST.
• Scan insertion and scan compression experience, including tools or technologies such as DFT Compiler, Mentor TestKompress, or SSN.
• Experience in ATPG vector generation, simulation, and debugging, including TetraMax or Fastscan.
• Experience in Verilog coding, testbench generation, and simulation.
• Memory BIST insertion and verification experience with embedded SRAM, CAM, eDRAM, or ROM.
• Boundary-scan verification and test-vector generation experience, with knowledge of IEEE 1149.1 and IEEE 1149.6.
• Basic knowledge of Test-STA and constraints.
• Strong background in IEEE 1687, IJTAG, ICL, PDL, and SSN.
• Ability to work in a multidisciplinary, cross-department environment.
• Knowledge of analog and digital circuit design and device physics fundamentals.
• Understanding of silicon processing, logical and physical synthesis, and transistor reliability principles.
• Excellent problem-solving, debugging, root-cause analysis, and communication skills.
• Ability to code using TCL, PERL, RUBY, PYTHON, C++, or similar.
• Bachelor's degree in Electrical, Electronic, or Computer Engineering and at least 5 years of relevant industry experience, or a Master's degree in one of these fields and at least 3 years of relevant industry experience.

Responsibilities

• Understand Broadcom and customer DFT feature requirements.
• Implement DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes, and other I/P DFT integration.
• Work with STA and DI engineers on design closure for test.
• Generate, verify, and debug test vectors before tape release.
• Validate and debug test vectors on ATE during silicon bring-up.
• Assist with silicon failure analysis, diagnostics, and yield improvement.
• Interface with customers and physical design, test engineering, and manufacturing teams located globally.
• Work with I/P DFT engineers and other stakeholders.
• Debug customer-returned parts on the ATE.

Benefits

• Discretionary annual bonus eligibility.
• Competitive new-hire equity grant and opportunity for annual equity awards, subject to plan documents and award agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level