DFT Engineer

Broadcom • Austin, TX

1d • Onsite

About The Position

Broadcom's ASIC Product Division is hiring a DFT Engineer for its Austin, Texas Development Center. The role covers DFT programs from chip-level specification through implementation and verification, with the goal of releasing products to production. Work includes SoC DFT insertion and verification, pattern generation, coverage improvement, post-silicon debugging, and yield improvement to meet product test metrics. The engineer will work with Physical Design and STA teams on DFT-mode timing closure and may interact directly with external customers.

Requirements

• Strong DFT background, such as IO and Analog DFT, ATPG, Scan, or BIST.
• Experience with scan insertion and scan compression, such as DFT Compiler, Mentor TestKompress, or SSN.
• Experience in ATPG vector generation, simulation, and debugging, using tools such as TetraMax or Fastscan.
• Experience in Verilog coding, testbench generation, and simulation.
• Experience inserting and verifying Memory BIST for embedded SRAM, CAM, eDRAM, or ROM.
• Experience with boundary scan verification and test-vector generation.
• Good knowledge of IEEE 1149.1 and IEEE 1149.6.
• Basic knowledge of Test-STA and constraints.
• Strong background in IEEE 1687, IJTAG, ICL, PDL, and SSN.
• Ability to work in a multidisciplinary, cross-department environment.
• Solid knowledge of analog and digital circuit design and device physics fundamentals.
• Good understanding of silicon processing, logical and physical synthesis, and transistor reliability principles.
• Excellent problem-solving, debugging, root-cause analysis, and communication skills.
• Ability to code using TCL, PERL, RUBY, PYTHON, C++, or similar.
• Bachelor's degree in Electrical, Electronic, or Computer Engineering and at least 5 years of relevant industry experience, or a master's degree in one of these fields and at least 3 years of relevant industry experience.

Responsibilities

• Understand Broadcom and customer DFT feature requirements.
• Implement DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes, and other IP DFT integration.
• Work with STA and DI engineers on design closure for test.
• Generate, verify, and debug test vectors before tape release.
• Validate and debug test vectors on ATE during silicon bring-up.
• Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
• Interface with customers and physical design and test engineering/manufacturing teams located globally.
• Work with IP DFT engineers and other stakeholders.
• Debug customer-returned parts on the ATE.

Benefits

• Discretionary annual bonus eligibility.
• Opportunity to receive a competitive new-hire equity grant and annual equity awards.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level