DFT Engineer

Broadcom • San Jose, CA

1d • Onsite

About The Position

Broadcom's ASIC Product Division is seeking a DFT Engineer at its San Jose, California Development Center. The engineer will work on DFT programs from chip-level specification through implementation and verification, culminating in product release to production. The role covers SoC DFT activities for APD designs, including test insertion and verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics. It also involves working with Physical Design and STA teams on DFT-mode timing closure and may include direct interaction with external customers. Coding in TCL, PERL, RUBY, PYTHON, C++ or similar is expected.

The position requires a strong background in DFT and associated test methods, including scan, ATPG, BIST, memory BIST, boundary scan, and related standards and tools. The engineer will collaborate with internal teams and global customer, physical-design, test-engineering, and manufacturing stakeholders, and will support silicon bring-up and returned-part debugging.

Candidates must have a bachelor's degree in Electrical, Electronic, or Computer Engineering and at least five years of relevant industry experience, or a master's degree in one of those fields and at least three years of relevant industry experience.

The annual base salary range is not provided in the posting. The position offers eligibility for a discretionary annual bonus and new-hire and annual equity awards. Broadcom lists medical, dental, and vision plans; 401(k) participation with company matching; an Employee Stock Purchase Program; an Employee Assistance Program; company-paid holidays; paid sick leave and vacation time; and leaves of absence in accordance with applicable laws.

Requirements

• Strong DFT background, such as IO and Analog DFT, ATPG, Scan, and BIST.
• Background in scan insertion and scan compression, including DFT Compiler, Mentor TestKompress, or SSN.
• Proficiency in ATPG vector generation, simulation, and debugging, including TetraMax or Fastscan.
• Experience in Verilog coding, testbench generation, and simulation.
• Memory BIST insertion and verification experience with embedded SRAM, CAM, eDRAM, or ROM.
• Boundary-scan verification and test-vector generation experience.
• Good knowledge of IEEE 1149.1 and IEEE 1149.6.
• Basic knowledge of Test-STA and constraints.
• Strong background in IEEE 1687, IJTAG, ICL, PDL, and SSN.
• Ability to work in a multidisciplinary, cross-department environment.
• Solid knowledge of analog and digital circuit design and device-physics fundamentals.
• Good understanding of silicon processing, logical and physical synthesis, and transistor reliability principles.
• Excellent problem-solving, debugging, root-cause-analysis, and communication skills.
• Ability to code using TCL, PERL, RUBY, PYTHON, C++, or similar.
• Bachelor's degree in Electrical, Electronic, or Computer Engineering and at least 5 years of relevant industry experience, or a master's degree in one of these fields and at least 3 years of relevant industry experience.

Responsibilities

• Understand Broadcom and customer DFT feature requirements.
• Implement DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes, and other IP DFT integration.
• Work with STA and DI engineers on design closure for test.
• Generate, verify, and debug test vectors before tape release.
• Validate and debug test vectors on ATE during silicon bring-up.
• Assist with silicon failure analysis, diagnostics, and yield-improvement efforts.
• Interface with customers and globally located physical-design and test-engineering/manufacturing teams.
• Work with IP DFT engineers and other stakeholders.
• Debug customer-returned parts on the ATE.

Benefits

• Eligibility for a discretionary annual bonus.
• Opportunity to receive a competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid family leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level