DFT Engineer

Tenstorrent•Fort Collins, CO

6h•$100,000 - $500,000•Hybrid

About The Position

Tenstorrent is hiring a Design for Test (DFT) Engineer to work on high-performance designs for advanced AI/ML architectures. The role covers implementation from RTL through tapeout across multiple chip IPs, with a focus on achieving high test coverage while reducing test cost, supporting debug and yield learning, and minimizing design intrusions. The engineer will collaborate with experienced colleagues across ASIC domains and with design, physical design, verification, test, and manufacturing teams. The position is hybrid and based in Santa Clara, California; Austin, Texas; or Fort Collins, Colorado. Candidates at different experience levels are welcome; level and offer will be aligned with the assessment during the interview process. Compensation ranges from $100,000 to $500,000, including base and variable compensation targets, with the actual offer depending on experience, skills, education, background, and location. Employment is contingent on eligibility to access U.S. export-controlled technology. Applicable export laws may make an offer contingent on citizenship or permanent residency status, or on obtaining prior license approval.

Requirements

BS, MS, or PhD in EE, ECE, CE, or CS.
At least 5 years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs.
Fluency in Verilog RTL for DFT logic, including lock-up latches, clock gates, and scan anchors.
Comfort with SystemVerilog and UVM.
Hands-on experience with ATPG and DFx insertion tools.
Experience with fault models including Stuck-at, Transition, Path Delay, IDDQ, and Cell-Aware.
Experience with low-power design flows.
Strong debugging and problem-solving skills across design hierarchies.
Ability to collaborate effectively with design, physical design, verification, and test teams.

Responsibilities

Implement and integrate DFT features, including scan, JTAG, compression, ASST, and MBIST, into RTL from early design through tapeout across multiple IPs.
Own ATPG, test coverage analysis, and gate-level simulation using tools such as Synopsys VCS and Verdi to achieve and maintain high-quality test coverage.
Plan, implement, and verify MBIST.
Work with Test Engineering on test planning, pattern delivery, and debug.
Develop and refine DFx flows and methodology that integrate with front-end and physical design flows while balancing coverage, test cost, and design intrusiveness.